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1. 发明授权

US08530326B2 Method of fabricating a dummy gate structure in a gate last process 有权
标题翻译：在门最后工艺中制造虚拟栅极结构的方法
公开(公告)号：US08530326B2
公开(公告)日：2013-09-10
申请号：US13538220
申请日：2012-06-29
申请人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng-Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng-Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要： A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
摘要翻译：一种半导体器件制造方法，包括在衬底的第一部分中形成多个栅极结构，其中所述多个栅极结构具有第一高度。第一金属栅极结构形成在衬底的第二部分中，第一金属栅极结构被隔离区包围。在基板的第二部分中形成多个虚拟栅极结构。多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。多个虚拟结构具有与多个栅极结构基本平面的顶表面，并且覆盖基板的第二部分的图案密度的至少5％。

2. 发明授权

US08125051B2 Device layout for gate last process 有权
标题翻译：门最后进程的设备布局
公开(公告)号：US08125051B2
公开(公告)日：2012-02-28
申请号：US12471091
申请日：2009-05-22
申请人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
发明人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
IPC分类号： H01L27/06 , H01L21/70 , H01L21/338 , H01L21/302
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0629 , H01L27/0635
摘要： A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，形成在第二区域中的隔离结构，形成在隔离结构中的至少一个接合器件第二区域，以及形成在第二区域中的隔离结构上方的停止结构。

3. 发明授权

US07803674B2 Methods for fabricating SOI devices 有权
标题翻译：制造SOI器件的方法
公开(公告)号：US07803674B2
公开(公告)日：2010-09-28
申请号：US12468131
申请日：2009-05-19
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
摘要翻译：提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。在衬底上形成第一绝缘层。在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。第一电介质层形成在每个半导体岛的一部分上。导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

4. 发明申请

US20100001332A1 INTEGRATING A CAPACITOR IN A METAL GATE LAST PROCESS 有权
标题翻译：在金属门最后过程中集成电容器
公开(公告)号：US20100001332A1
公开(公告)日：2010-01-07
申请号：US12256132
申请日：2008-10-22
申请人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
发明人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
IPC分类号： H01L29/92 , H01L21/34
CPC分类号： H01L27/0629 , H01L27/11 , H01L29/94
摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料电极。

5. 发明申请

US20120270379A1 METHOD OF FABRICATING A DUMMY GATE STRUCTURE IN A GATE LAST PROCESS 有权
标题翻译：在门窗最后过程中制造多孔门结构的方法
公开(公告)号：US20120270379A1
公开(公告)日：2012-10-25
申请号：US13538220
申请日：2012-06-29
申请人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要： A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
摘要翻译：一种半导体器件制造方法，包括在衬底的第一部分中形成多个栅极结构，其中所述多个栅极结构具有第一高度。第一金属栅极结构形成在衬底的第二部分中，第一金属栅极结构被隔离区包围。在基板的第二部分中形成多个虚拟栅极结构。多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。多个虚拟结构具有与多个栅极结构基本平面的顶表面，并且覆盖基板的第二部分的图案密度的至少5％。

6. 发明申请

US20090218623A1 SOI DEVICES AND METHODS FOR FABRICATING THE SAME 有权
公开(公告)号：US20090218623A1
公开(公告)日：2009-09-03
申请号：US12468137
申请日：2009-05-19
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

7. 发明授权

US07550795B2 SOI devices and methods for fabricating the same 有权
标题翻译： SOI器件及其制造方法
公开(公告)号：US07550795B2
公开(公告)日：2009-06-23
申请号：US11477953
申请日：2006-06-30
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L29/76
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
摘要翻译：提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。在衬底上形成第一绝缘层。在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。第一电介质层形成在每个半导体岛的一部分上。导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

8. 发明授权

US08368136B2 Integrating a capacitor in a metal gate last process 有权
标题翻译：将电容器集成在金属栅极最后工艺中
公开(公告)号：US08368136B2
公开(公告)日：2013-02-05
申请号：US12256132
申请日：2008-10-22
申请人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
发明人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
IPC分类号： H01L27/04
CPC分类号： H01L27/0629 , H01L27/11 , H01L29/94
摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料电极。

9. 发明申请

US20100052060A1 Dummy gate structure for gate last process 有权
标题翻译：门最后工序的虚拟门结构
公开(公告)号：US20100052060A1
公开(公告)日：2010-03-04
申请号：US12455509
申请日：2009-06-03
申请人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号： H01L27/06 , H01L21/77
CPC分类号： H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要： A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.
摘要翻译：提供一种半导体器件，其包括具有第一部分和第二部分的半导体衬底，形成在衬底的第一部分中的晶体管，每个晶体管具有具有高k电介质和金属栅极的栅极结构，形成器件元件在衬底的第二部分中，器件元件被隔离区域隔离，抛光停止件形成在隔离区域附近，并且具有与第一区域中的晶体管的栅极结构的表面基本平面的表面。

10. 发明申请

US20090298243A1 SOI DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译： SOI器件及其制造方法
公开(公告)号：US20090298243A1
公开(公告)日：2009-12-03
申请号：US12468131
申请日：2009-05-19
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
摘要翻译：提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。在衬底上形成第一绝缘层。在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。第一电介质层形成在每个半导体岛的一部分上。导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

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