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1. 发明授权

US09054025B2 Process for controlling shallow trench isolation step height 有权
标题翻译：控制浅沟槽隔离台阶高度的工艺
公开(公告)号：US09054025B2
公开(公告)日：2015-06-09
申请号：US12478135
申请日：2009-06-04
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
IPC分类号： H01L21/66 , H01L21/762
CPC分类号： H01L22/20 , H01L21/76224 , H01L22/12
摘要： A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.
摘要翻译：公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

2. 发明申请

US20100112732A1 NOVEL PROCESS FOR CONTROLLING SHALLOW TRENCH ISOLATION STEP HEIGHT 有权
标题翻译：用于控制SHALLOW TRENCH隔离步骤高度的新方法
公开(公告)号：US20100112732A1
公开(公告)日：2010-05-06
申请号：US12478135
申请日：2009-06-04
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L21/76224 , H01L22/12
摘要： A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.
摘要翻译：公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

3. 发明授权

US08349680B2 High-k metal gate CMOS patterning method 有权
标题翻译：高k金属栅极CMOS图案化方法
公开(公告)号：US08349680B2
公开(公告)日：2013-01-08
申请号：US12536629
申请日：2009-08-06
申请人： Kong-Beng Thei , Harry Chuang , Ryan Chia-Jen Chen , Su-Chen Lai , Yi-Shien Mor , Yi-Hsing Chen , Gary Shen , Yu Chao Lin
发明人： Kong-Beng Thei , Harry Chuang , Ryan Chia-Jen Chen , Su-Chen Lai , Yi-Shien Mor , Yi-Hsing Chen , Gary Shen , Yu Chao Lin
IPC分类号： H01L21/8238
CPC分类号： H01L21/31645 , H01L21/31604 , H01L21/823842
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成第一金属层第一金属层具有第一功函数，在第一有源区中的第一金属层上形成掩模层，使用掩模层去除第一金属层和第二有源区中的覆盖层的至少一部分并且在所述第二有源区域中的所述部分去除的覆盖层上形成第二金属层，所述第二金属层具有第二功函数。

4. 发明授权

US07923321B2 Method for gap filling in a gate last process 有权
标题翻译：最后一道工序间隙填充方法
公开(公告)号：US07923321B2
公开(公告)日：2011-04-12
申请号：US12487894
申请日：2009-06-19
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen
IPC分类号： H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823842 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66628
摘要： A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.
摘要翻译：提供一种用于制造半导体器件的方法，该半导体器件包括提供具有第一区域和第二区域的半导体衬底，在衬底上形成高k电介质层，在高k电介质层上形成硅层，形成硬的掩模层，图案化硬掩模层，硅层和高k电介质层，以分别在第一和第二区域上形成第一和第二栅极结构，在第一和第二区域上形成接触蚀刻停止层（CESL）和第二栅极结构，通过蚀刻工艺修改CESL的轮廓，在改性CESL上形成层间电介质（ILD），在ILD上进行化学机械抛光（CMP）以暴露第一和第二栅极结构的硅层第二栅极结构，并分别从第一和第二栅极结构去除硅层，并用金属栅极结构代替硅层。

5. 发明申请

US20100065915A1 CHEMICAL MECHANICAL POLISHING (CMP) METHOD FOR GATE LAST PROCESS 有权
标题翻译：用于门控最后过程的化学机械抛光（CMP）方法
公开(公告)号：US20100065915A1
公开(公告)日：2010-03-18
申请号：US12423422
申请日：2009-04-14
申请人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
发明人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
IPC分类号： H01L27/092 , H01L21/70
CPC分类号： H01L21/823828 , H01L21/31053 , H01L21/823437 , H01L29/66545 , Y10S438/926
摘要： A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.
摘要翻译：提供了一种制造半导体器件的方法，其包括提供半导体衬底，形成多个晶体管，每个晶体管具有虚拟栅极结构，在包括虚拟栅极结构的衬底上形成接触蚀刻停止层（CESL），形成第一电介质层，以填充相邻虚拟栅极结构之间的每个区域的一部分，在CESL和第一介电层上形成化学机械抛光（CMP）阻挡层，在CMP停止层上形成第二介电层，对CMP 所述第二电介质层在所述CMP停止层处基本上停止，并且执行过度抛光以暴露所述伪栅极结构。

6. 发明申请

US20100311231A1 METHOD FOR A GATE LAST PROCESS 有权
标题翻译：门过程的方法
公开(公告)号：US20100311231A1
公开(公告)日：2010-12-09
申请号：US12478358
申请日：2009-06-04
申请人： Kong-Beng Thei , Harry Chuang , Su-Chen Lai , Gary Shen
发明人： Kong-Beng Thei , Harry Chuang , Su-Chen Lai , Gary Shen
IPC分类号： H01L21/336 , H01L21/306 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66583
摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括提供基板; 在所述衬底上形成一个或多个栅极结构; 在衬底上形成缓冲层，包括在一个或多个栅极结构上; 在缓冲层上形成蚀刻停止层; 在所述蚀刻停止层上形成层间电介质（ILD）层; 以及去除所述缓冲层的一部分，所述蚀刻停止层的一部分以及所述一个或多个栅极结构上的所述ILD层的一部分。

7. 发明申请

US20100048013A1 NOVEL HIGH-K METAL GATE CMOS PATTERNING METHOD 有权
标题翻译：新型高K金属栅CMOS图案方法
公开(公告)号：US20100048013A1
公开(公告)日：2010-02-25
申请号：US12536629
申请日：2009-08-06
申请人： Kong-Beng Thei , Harry Chuang , Ryan Chia-Jen Chen , Su-Chen Lai , Yi-Shien Mor , Yi-Hsing Chen , Gary Shen , Y. C. Lin
发明人： Kong-Beng Thei , Harry Chuang , Ryan Chia-Jen Chen , Su-Chen Lai , Yi-Shien Mor , Yi-Hsing Chen , Gary Shen , Y. C. Lin
IPC分类号： H01L21/28
CPC分类号： H01L21/31645 , H01L21/31604 , H01L21/823842
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成第一金属层第一金属层具有第一功函数，在第一有源区中的第一金属层上形成掩模层，使用掩模层去除第一金属层和第二有源区中的覆盖层的至少一部分并且在所述第二有源区域中的所述部分去除的覆盖层上形成第二金属层，所述第二金属层具有第二功函数。

8. 发明授权

US08390072B2 Chemical mechanical polishing (CMP) method for gate last process 有权
标题翻译：门最后工艺的化学机械抛光（CMP）方法
公开(公告)号：US08390072B2
公开(公告)日：2013-03-05
申请号：US13156558
申请日：2011-06-09
申请人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
发明人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823828 , H01L21/31053 , H01L21/823437 , H01L29/66545 , Y10S438/926
摘要： A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.
摘要翻译：提供了一种制造半导体器件的方法，其包括提供半导体衬底，形成多个晶体管，每个晶体管具有虚拟栅极结构，在包括虚拟栅极结构的衬底上形成接触蚀刻停止层（CESL），形成第一电介质层，以填充相邻虚拟栅极结构之间的每个区域的一部分，在CESL和第一介电层上形成化学机械抛光（CMP）阻挡层，在CMP停止层上形成第二介电层，对CMP 所述第二电介质层在所述CMP停止层处基本上停止，并且执行过度抛光以暴露所述伪栅极结构。

9. 发明申请

US20110233683A1 CHEMICAL MECHANICAL POLISHING (CMP) METHOD FOR GATE LAST PROCESS 有权
标题翻译：用于门控最后过程的化学机械抛光（CMP）方法
公开(公告)号：US20110233683A1
公开(公告)日：2011-09-29
申请号：US13156558
申请日：2011-06-09
申请人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
发明人： Harry Chuang , Kong-Beng Thei , Su-Chen Lai , Gary Shen
IPC分类号： H01L27/092 , H01L29/772
CPC分类号： H01L21/823828 , H01L21/31053 , H01L21/823437 , H01L29/66545 , Y10S438/926
摘要： A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.
摘要翻译：提供了一种制造半导体器件的方法，其包括提供半导体衬底，形成多个晶体管，每个晶体管具有虚拟栅极结构，在包括虚拟栅极结构的衬底上形成接触蚀刻停止层（CESL），形成第一电介质层，以填充相邻虚拟栅极结构之间的每个区域的一部分，在CESL和第一介电层上形成化学机械抛光（CMP）阻挡层，在CMP停止层上形成第二介电层，对CMP 所述第二电介质层在所述CMP停止层处基本上停止，并且执行过度抛光以暴露所述伪栅极结构。

10. 发明授权

US07985690B2 Method for a gate last process 有权
标题翻译：最后一个进程的方法
公开(公告)号：US07985690B2
公开(公告)日：2011-07-26
申请号：US12478358
申请日：2009-06-04
申请人： Kong-Beng Thei , Harry Chuang , Su-Chen Lai , Gary Shen
发明人： Kong-Beng Thei , Harry Chuang , Su-Chen Lai , Gary Shen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/7833 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66583
摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括提供基板; 在所述衬底上形成一个或多个栅极结构; 在衬底上形成缓冲层，包括在一个或多个栅极结构上; 在缓冲层上形成蚀刻停止层; 在所述蚀刻停止层上形成层间电介质（ILD）层; 以及去除所述缓冲层的一部分，所述蚀刻停止层的一部分以及所述一个或多个栅极结构上的所述ILD层的一部分。

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