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1. 发明授权

US06833311B2 Manufacturing method for a shallow trench isolation region with high aspect ratio 有权
公开(公告)号：US06833311B2
公开(公告)日：2004-12-21
申请号：US10426327
申请日：2003-04-30
申请人： Hsin-Jung Ho , Chang Rong Wu , Tzu En Ho
发明人： Hsin-Jung Ho , Chang Rong Wu , Tzu En Ho
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A manufacturing method for a shallow trench isolation region with high aspect ratio. The method comprises the steps of providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by high density plasma chemical vapor deposition (HDPCVD), removing the majority of the first insulation layer outside the trench by spray type etching, and forming a second insulation layer on the first insulation layer by low pressure CVD to fill the trench. According to the present invention, a void-free shallow trench isolation with high aspect ration can be achieved.

2. 发明授权

US06833309B2 Method of manufacturing a semiconductor device 失效
公开(公告)号：US06833309B2
公开(公告)日：2004-12-21
申请号：US10832392
申请日：2004-04-27
申请人： Hiroshi Fukuda
发明人： Hiroshi Fukuda
IPC分类号： H01L2176
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Upon formation of semiconductor micro patterns, an interlayer alignment error occurs due to asymmetry of each alignment mark. Prior to alignment of a mask with a wafer, the asymmetry of each alignment mark is measured according to the principle of a scatterometry, and the alignment is performed in consideration of the result of measurement to execute exposure. Thus, high-accuracy alignment can be carried out without sacrificing throughput, and the performance of a semiconductor device is improved. Further, manufacturing yields can be enhanced and a reduction in cost can be realized.

3. 发明授权

US06828213B2 Method to improve STI nano gap fill and moat nitride pull back 有权
标题翻译：改善STI纳米间隙填充和护环氮化物拉回的方法
公开(公告)号：US06828213B2
公开(公告)日：2004-12-07
申请号：US10376021
申请日：2003-02-28
申请人： Freidoon Mehrad , Zhihao Chen , Majid M. Mansoori
发明人： Freidoon Mehrad , Zhihao Chen , Majid M. Mansoori
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.
摘要翻译：通过生长衬垫氧化物，在衬垫氧化物上沉积氮化物层的步骤和护壁护理图案，护壁蚀刻和护城河清洁的步骤之后，提供了改善浅沟槽隔离（STI）间隙填充和齿隙氮化物拉回的方法，生长热氧化物的步骤，使一部分护环氮化物脱气; 沉积薄氮化物衬垫，蚀刻氮化物以在STI沟槽中形成薄的侧壁氮化物; 并在STI衬垫氧化和沉积氧化物以填充沟槽之前进行氧化物氢氟酸（HF）酸蒸气。

4. 发明授权

US06828210B2 Method of forming a device isolation trench in an integrated circuit device 有权
标题翻译：在集成电路器件中形成器件隔离沟槽的方法
公开(公告)号：US06828210B2
公开(公告)日：2004-12-07
申请号：US10080884
申请日：2002-02-22
申请人： Do-Hyung Kim , Sung-Bong Kim , Jung-In Hong
发明人： Do-Hyung Kim , Sung-Bong Kim , Jung-In Hong
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method of forming a trench isolation in a semiconductor substrate is described, which comprises the steps of forming a trench on the substrate, forming a diffusion barrier insulating layer, forming a thermal oxide layer both sidewall and bottom of the trench contacted with the diffusion barrier insulating layer, forming a nitride liner, and forming trench isolation material to fill the trench. A multi-structure of the barrier layer and the thermal oxide layer is provided between the nitride liner and the trench, resulting in minimization of transistor characteristic deterioration. A thin thermal oxide layer is formed to achieve improved trench etching profile.
摘要翻译：描述了在半导体衬底中形成沟槽隔离的方法，其包括以下步骤：在衬底上形成沟槽，形成扩散阻挡绝缘层，形成与扩散阻挡层接触的沟槽的侧壁和底部的热氧化物层绝缘层，形成氮化物衬垫，以及形成沟槽隔离材料以填充沟槽。在氮化物衬垫和沟槽之间设置阻挡层和热氧化物层的多结构，导致晶体管特性劣化的最小化。形成薄的热氧化物层以实现改进的沟槽蚀刻轮廓。

5. 发明授权

US06815309B2 Support-integrated donor wafers for repeated thin donor layer separation 有权
标题翻译：用于重复薄施主层分离的支撑集成供体晶片
公开(公告)号：US06815309B2
公开(公告)日：2004-11-09
申请号：US10327790
申请日：2002-12-23
申请人： Fabrice Letertre , Thibaut Maurice
发明人： Fabrice Letertre , Thibaut Maurice
IPC分类号： H01L2176
CPC分类号： H01L21/2007 , H01L21/76251 , Y10S438/954 , Y10S438/964
摘要： Processes that may be used in producing electronic, opotoelectronic, or optical components may be provided. The processes may involve preparing a reusable donor wafer for donating a thin layer of semiconductor material by assembling a donor layer of a semiconductor material having a thickness of plural thin layers onto a support layer of. The semiconductor material for the support layer may be selected to be less precious or to have a lower quality than the donor layer. The support layer may have sufficient mechanical characteristics for supporting the donor layer during desired semiconductor processing treatments.
摘要翻译：可以提供可用于生产电子，光电子或光学部件的方法。该方法可以包括通过将具有多个薄层的厚度的半导体材料的施主层组装到其上的支撑层上来制备用于提供半导体材料薄层的可重复使用的施主晶片。可以选择用于支撑层的半导体材料不太贵，或者具有比施主层更低的质量。在期望的半导体加工处理期间，支撑层可以具有用于支撑施主层的足够的机械特性。

6. 发明授权

US06815308B2 Use of a dual-tone resist to form photomasks including alignment mark protection, intermediate semiconductor device structures and bulk semiconductor device substrates 失效
公开(公告)号：US06815308B2
公开(公告)日：2004-11-09
申请号：US10219168
申请日：2002-08-15
申请人： Richard D. Holscher , Niroomand Ardavan
发明人： Richard D. Holscher , Niroomand Ardavan
IPC分类号： H01L2176
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002 , Y10S438/942 , Y10S438/947 , Y10S438/975 , H01L2924/00
摘要： An alignment mark mask element protects an underlying alignment mark during subsequent processing of the fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.

7. 发明授权

US06812115B2 Method of filling an opening in a material layer with an insulating material 有权
标题翻译：用绝缘材料填充材料层中的开口的方法
公开(公告)号：US06812115B2
公开(公告)日：2004-11-02
申请号：US10403584
申请日：2003-03-31
申请人： Karsten Wieczorek , Stephan Kruegel , Michael Raab
发明人： Karsten Wieczorek , Stephan Kruegel , Michael Raab
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , Y10S438/933
摘要： The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.
摘要翻译：用介电材料填充0.25μm以下的沟槽可能导致形成空隙。通常，可以通过氧化封闭空隙。当沟槽包括不可氧化的侧壁部分时，可能导致不充分的闭合。因此，在沉积体电介质之前，可共形沉积可氧化间隔层，使得沟槽的侧壁可以沿着沟槽的整个深度被氧化，从而允许空隙的完全封闭。

8. 发明授权

US06809006B2 Method of semiconductor device isolation 失效
标题翻译：半导体器件隔离方法
公开(公告)号：US06809006B2
公开(公告)日：2004-10-26
申请号：US10242219
申请日：2002-09-12
申请人： Bong Soo Kim , Jeong Bok Kim
发明人： Bong Soo Kim , Jeong Bok Kim
IPC分类号： H01L2176
CPC分类号： H01L21/76237 , H01L21/26506 , H01L21/76235
摘要： a method of semiconductor device isolation, which can minimize an design rule of trenches comprising the steps of providing a substrate where a device isolation region was defined; removing the device isolation region of the substrate using a photolithography process to form trenches; implanting ions into the substrate having the trenches to form an impurity layer having a uniform depth relative to the surface of the substrate; thermally oxidizing the substrate having the impurity layer to form an oxide film; and removing the oxide film.
摘要翻译：半导体器件隔离的方法，其可以最小化沟槽的设计规则，包括以下步骤：提供限定器件隔离区域的衬底; 使用光刻工艺去除衬底的器件隔离区以形成沟槽; 将离子注入具有沟槽的衬底中以形成相对于衬底表面具有均匀深度的杂质层; 热氧化具有杂质层的基板以形成氧化膜; 并除去氧化膜。

9. 发明授权

US06809005B2 Method to fill deep trench structures with void-free polysilicon or silicon 失效
标题翻译：用无孔多晶硅或硅填充深沟槽结构的方法
公开(公告)号：US06809005B2
公开(公告)日：2004-10-26
申请号：US10386880
申请日：2003-03-12
申请人： Rajiv Ranade , Gangadhara S. Mathad , Kevin K. Chan , Subhash B. Kulkarni
发明人： Rajiv Ranade , Gangadhara S. Mathad , Kevin K. Chan , Subhash B. Kulkarni
IPC分类号： H01L2176
CPC分类号： H01L27/1087 , H01L21/0237 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/763 , H01L29/66181
摘要： The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.
摘要翻译：本发明提供了在其中制造基本上无空隙填料的沟槽结构的方法。填料可以从诸如沿沟槽的侧壁形成的多晶硅的衬垫材料生长。先前形成的空隙可以通过暴露空隙和生长外延硅来治愈。

10. 发明授权

US06806161B2 Process for preparing insulating material having low dielectric constant 有权
公开(公告)号：US06806161B2
公开(公告)日：2004-10-19
申请号：US09844553
申请日：2001-04-27
申请人： Min-Jin Ko , Hye-Yeong Nam , Dong-Seok Shin , Myung-Sun Moon , Jung-Won Kang
发明人： Min-Jin Ko , Hye-Yeong Nam , Dong-Seok Shin , Myung-Sun Moon , Jung-Won Kang
IPC分类号： H01L2176
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/31695 , H01L21/76801 , H01L2924/0002 , Y10S438/96 , H01L2924/00
摘要： The present invention relates to low dielectric materials essential for a semiconductor having high density and high performance of the next generation, particularly to a process for preparing a porous interlayer insulating film having low dielectric constant containing pores with a size of a few nanometers or less. The present invention provides a process for preparing a porous wiring interlayer insulating film having very low dielectric constant for a semiconductor device comprising the steps of a) preparing a mixed complex of pore-forming organic molecules and a matrix resin, b) coating the mixed complex on a substrate, and c) heating the mixed complex to remove the organic molecules therefrom, thereby forming pores inside the complex. The porous wiring interlayer insulating film having very low dielectric constant prepared according to the process of the present invention has reduced phase-separation, excellent processibility, isotropic structure and very small pores with a size of a few nanometers or less.

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