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1. 发明授权

US06350662B1 Method to reduce defects in shallow trench isolations by post liner anneal 有权
标题翻译：通过后衬板退火来减少浅沟槽隔离缺陷的方法
公开(公告)号：US06350662B1
公开(公告)日：2002-02-26
申请号：US09357244
申请日：1999-07-19
申请人： Kong-Beng Thei , Kuei-Ying Lee , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Kong-Beng Thei , Kuei-Ying Lee , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method to form shallow trench isolations with reduced substrate defects by using a nitrogen anneal is achieved. A silicon substrate is provided. The silicon substrate is etched where not protected by a photoresist mask to form shallow trenches where shallow trench isolations are planned. A liner oxide layer is grown on the interior surfaces of the shallow trenches. The silicon substrate and the liner oxide layer are annealed to reduce or eliminate defects, dislocations, interface traps, and stress in the silicon substrate. An isolation oxide layer is deposited overlying the liner oxide layer and completely filling the shallow trenches. The isolation oxide layer is etched down to the top surface of the silicon substrate and thereby forms the shallow trench isolations. The integrated circuit device is completed.
摘要翻译：实现了通过使用氮退火形成具有减少的衬底缺陷的浅沟槽隔离的方法。提供硅衬底。蚀刻硅衬底，其中未被光致抗蚀剂掩模保护以形成浅沟槽，其中规划浅沟槽隔离。在浅沟槽的内表面上生长衬里氧化物层。对硅衬底和衬里氧化物层进行退火以减少或消除硅衬底中的缺陷，位错，界面陷阱和应力。隔离氧化物层沉积在衬垫氧化物层上并且完全填充浅沟槽。隔离氧化物层被蚀刻到硅衬底的顶表面，从而形成浅沟槽隔离。集成电路装置完成。

2. 发明授权

US6046103A Borderless contact process for a salicide devices 有权
标题翻译：自杀式装置的无边界接触过程
公开(公告)号：US6046103A
公开(公告)日：2000-04-04
申请号：US365983
申请日：1999-08-02
申请人： Kong-Beng Thei , Ming-Dar Lei , Shou-Gwo Wuu
发明人： Kong-Beng Thei , Ming-Dar Lei , Shou-Gwo Wuu
IPC分类号： H01L21/285 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/28518 , H01L21/31116 , H01L21/76834
摘要： A process for forming a borderless contact opening to an active device region, overlaid with a metal silicide layer, has been developed. The borderless contact opening is formed in a composite insulator layer, comprised with an overlying, thick ILD layer, and a thin, underlying silicon oxynitride layer. The thin silicon oxynitride layer, used as a etch stop layer, during the anisotropic RIE procedure used to form the borderless contact opening, is deposited at a temperature below 350.degree. C., to prevent agglomeration of the metal silicide layer.
摘要翻译：已经开发了用金属硅化物层覆盖的有源器件区域形成无边界接触开口的方法。无边界接触开口形成在复合绝缘体层中，其包括上覆的厚的ILD层和薄的下面的氮氧化硅层。在用于形成无边界接触开口的各向异性RIE程序期间用作蚀刻停止层的薄氧氮化硅层在低于350℃的温度下沉积，以防止金属硅化物层的附聚。

3. 发明授权

US06335249B1 Salicide field effect transistors with improved borderless contact structures and a method of fabrication 有权
标题翻译：具有改进的无边界接触结构的杀菌剂场效应晶体管和制造方法
公开(公告)号：US06335249B1
公开(公告)日：2002-01-01
申请号：US09498981
申请日：2000-02-07
申请人： Kong-Beng Thei , Ming-Ta Lei , Shou-Gwo Wuu
发明人： Kong-Beng Thei , Ming-Ta Lei , Shou-Gwo Wuu
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/28518 , H01L29/665
摘要： A process for making improved borderless contact structure to salicide field effect transistors (FETs) has been achieved. Salicide FETs are formed on device areas surrounded by a shallow trench isolation (STI) using a first rapid thermal anneal (RTA-1) to form a metal silicide on the source/drain contacts and the gate electrodes, and a second rapid thermal anneal (RTA-2) is delayed until after forming a borderless contact opening structures to the source/drain areas of the FETs. An etch stop (Si3N4) layer and an interlevel dielectric (ILD) layer is deposited, and borderless contact openings, extending over the STI, are etched in the ILD and etch stop layers to the source/drain areas. The contact openings across the substrate must be over-etched to insure that all contacts are open. This results in over-etched region in the STI at the source/drain-STI interface that result in source/drain-to-substrate shorts when metal plugs are formed in the contact openings.
摘要翻译：已经实现了对自对准硅化物场效应晶体管（FET）进行改进的无边界接触结构的方法。使用第一快速热退火（RTA-1）在由浅沟槽隔离（STI）围绕的器件区域上形成硅化物FET，以在源/漏接触和栅电极上形成金属硅化物，以及第二快速热退火 RTA-2）延迟直到形成无界面接触开口结构到FET的源极/漏极区域。沉积蚀刻停止层（Si3N4）层和层间电介质（ILD）层，并且在IL上延伸的无边界接触开口在ILD中蚀刻，并将停止层蚀刻到源极/漏极区域。必须对衬底上的接触孔进行过蚀刻，以确保所有接触都是开放的。这导致在源极/漏极-CS接口处的STI中的过蚀刻区域，当在接触开口中形成金属插塞时，其导致源极/漏极到衬底短路。

4. 发明授权

US06710413B2 Salicide field effect transistors with improved borderless contact structures and a method of fabrication 失效
标题翻译：具有改进的无边界接触结构的杀菌剂场效应晶体管和制造方法
公开(公告)号：US06710413B2
公开(公告)日：2004-03-23
申请号：US10084082
申请日：2002-02-27
申请人： Kong-Beng Thei , Ming-Ta Lei , Shou-Gwo Wuu
发明人： Kong-Beng Thei , Ming-Ta Lei , Shou-Gwo Wuu
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/28518 , H01L29/665
摘要： An improved borderless contact structure for salicide field effect transistors (FETs) has been achieved. Salicide FETs are formed on device areas surrounded by a shallow trench isolation (STI) using a first rapid thermal anneal to form a metal silicide on the source/drain contacts and the gate electrodes. An interlevel dielectric (ILD) layer is deposited, and borderless contact openings, extending over the STI, are etched in the ILD to the source/drain areas. When the contact openings are etched, this results in over-etched regions in the STI at the source/drain-STI interface that result in source/drain-to-substrate shorts when metal plugs are formed in the contact openings. A contact opening implant is used to dope the junction profile in the source/drain contact around the STI over-etched region to prevent electrical shorts. The second RTA is then used to concurrently reduce the silicide sheet resistance and to electrically activate the contact opening implanted dopant.
摘要翻译：已经实现了改善的无界面接触结构，用于自对准场效应晶体管（FET）。在使用第一快速热退火的浅沟槽隔离（STI）包围的器件区域上形成硅化物FET，以在源/漏接触件和栅电极上形成金属硅化物。沉积层间电介质（ILD）层，并且在STI上延伸的无边界接触开口在ILD中被蚀刻到源极/漏极区域。当接触开口被蚀刻时，这导致在源极/漏极-CS界面处的STI中的过度蚀刻区域，当在接触开口中形成金属插塞时，导致源极/漏极到衬底的短路。接触开口植入物用于掺杂STI过度蚀刻区域周围的源极/漏极接触中的接合剖面，以防止电气短路。然后，第二RTA用于同时降低硅化物薄层电阻并且电激活注入的接触开口的掺杂剂。

5. 发明授权

US06265271B1 Integration of the borderless contact salicide process 有权
标题翻译：整合无边界接触自杀过程
公开(公告)号：US06265271B1
公开(公告)日：2001-07-24
申请号：US09489967
申请日：2000-01-24
申请人： Kong-Beng Thei , Shou-Gwo Wuu
发明人： Kong-Beng Thei , Shou-Gwo Wuu
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28518
摘要： A method for integrating salicide and borderless contact processes while avoiding current leakage at the shallow trench isolation edge is described. Shallow trench isolation (STI) regions are formed in a semiconductor substrate electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A metal layer is deposited over the gate electrode and associated source and drain regions. A first annealing of the semiconductor substrate transforms the metal layer into a metal silicide layer over the gate electrode and source and drain regions. The metal layer which is not transformed into a metal silicide overlying the dielectric spacers and shallow trench isolation regions is removed. An etch stop layer is deposited over the surface of the semiconductor substrate. A second annealing changes the metal silicide layer to a phase having lower resistance and also densifies the etch stop layer. An interlevel dielectric layer is deposited over the densified etch stop layer. A borderless contact opening is formed through the interlevel dielectric layer and the etch stop layer to one of the source and drain regions and the contact opening is filled with a conducting layer to complete fabrication of the integrated circuit device.
摘要翻译：描述了一种整合自杀化合物和无边界接触过程同时避免浅沟槽隔离边缘处的电流泄漏的方法。在半导体衬底中形成浅沟槽隔离（STI）区域，以将活性区域与其它有效区域电隔离。在有源区域中形成栅电极和相关源极和漏极区，其中在栅电极的侧壁上形成有电介质间隔物。在栅极电极和相关的源极和漏极区域上沉积金属层。半导体衬底的第一退火将金属层转变成栅极电极和源极和漏极区域上的金属硅化物层。去除未转换成覆盖电介质间隔物和浅沟槽隔离区域的金属硅化物的金属层。在半导体衬底的表面上沉积蚀刻停止层。第二次退火将金属硅化物层改变为具有较低电阻的相，并且还使蚀刻停止层致密化。在致密化的蚀刻停止层上沉积层间电介质层。通过层间介质层和蚀刻停止层形成无边界的接触开口到源区和漏区中的一个，并且接触开口填充有导电层以完成集成电路器件的制造。

6. 发明授权

US06110793A Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits 失效
标题翻译：用于制造具有保形衬垫氧化物的沟槽隔离和用于集成电路的顶部和底部圆角的方法
公开(公告)号：US06110793A
公开(公告)日：2000-08-29
申请号：US104033
申请日：1998-06-24
申请人： Kuei-Ying Lee , Kong-Beng Thei , Bou-Fun Chen
发明人： Kuei-Ying Lee , Kong-Beng Thei , Bou-Fun Chen
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76235
摘要： A method for forming an improved trench isolation having a conformal liner oxide and rounded top and bottom corners in the trench was achieved. The conformal liner oxide improves the CVD gap-filling capabilities for these deep submicron wide trenches, and the rounded corners improve the electrical characteristics of the devices in the adjacent device areas. After etching trenches with vertical sidewalls in the silicon substrate, a two-step oxidation process is used to form the conformal liner oxide. A first oxidation step using a low-oxygen flow rate and a low temperature (about 850 to 920.degree. C.) is used to achieve rounded bottom corners. A second oxidation step at a low-oxygen flow rate and a higher temperature (about 1000 to 1150.degree. C.) is used to achieve rounded top corners. The two-step process also results in a more conformal liner oxide. The trenches are then filled with a CVD oxide and polished or etched back to an oxidation-barrier layer/etch-stop layer over the device areas to complete the trench isolation.
摘要翻译：实现了在沟槽中形成具有共形衬垫氧化物和圆形顶部和底部角的改进的沟槽隔离的方法。保形衬垫氧化物改善了这些深亚微米宽沟槽的CVD间隙填充能力，并且圆角提高了相邻器件区域中器件的电气特性。在硅衬底中用垂直侧壁蚀刻沟槽之后，使用两步氧化工艺来形成保形衬里氧化物。使用低氧气流速度和低温（约850-920℃）的第一氧化步骤来实现圆角的底角。使用低氧流速和较高温度（约1000至1150℃）的第二氧化步骤来实现圆角顶角。两步法也导致更适形的衬里氧化物。然后用CVD氧化物填充沟槽并在器件区域上抛光或蚀刻回到氧化阻挡层/蚀刻停止层以完成沟槽隔离。

7. 发明授权

US06214698B1 Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer 有权
标题翻译：采用间隙填充掺杂氧化硅介质层的浅沟槽隔离方法
公开(公告)号：US06214698B1
公开(公告)日：2001-04-10
申请号：US09480270
申请日：2000-01-11
申请人： Jhon-Jhy Liaw , Jin-Yuan Lee , Kuei-Ying Lee , Chu-Yun Fu , Kong-Beng Thei
发明人： Jhon-Jhy Liaw , Jin-Yuan Lee , Kuei-Ying Lee , Chu-Yun Fu , Kong-Beng Thei
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for filling a trench within a substrate. First a substrate is provided having a trench formed therein. The trench has a bottom surface and opposing side walls. An undoped silicon glass liner is then thermally grown to coat the bottom surface and side walls of the trench. An undoped silicon oxide layer is then deposited over the undoped silicon glass liner. A boron doped silicon oxide layer is then deposited over the undoped silicon oxide layer, filling the trench. The boron doped silicon oxide layer is then heated to reflow the boron doped silicon oxide to fill any void initially formed within the boron doped silicon oxide layer within the trench, thereby eliminating any void so formed.
摘要翻译：一种填充衬底内的沟槽的方法。首先，提供具有形成在其中的沟槽的衬底。沟槽具有底面和相对的侧壁。然后将未掺杂的硅玻璃衬里热生长以涂覆沟槽的底表面和侧壁。然后将未掺杂的氧化硅层沉积在未掺杂的硅玻璃衬垫上。然后将硼掺杂的氧化硅层沉积在未掺杂的氧化硅层上，填充沟槽。然后加热硼掺杂的氧化硅层以回流硼掺杂的氧化硅以填充初始形成在沟槽内的硼掺杂的氧化硅层内的任何空隙，从而消除如此形成的任何空隙。

8. 发明授权

US09099556B2 Transistor having an active region with wing structure 有权
标题翻译：晶体管具有机翼结构的有源区域
公开(公告)号：US09099556B2
公开(公告)日：2015-08-04
申请号：US13213409
申请日：2011-08-19
申请人： Chen-Liang Chu , Fei-Yuh Chen , Yi-Sheng Chen , Shih-Kuang Hsiao , Chun Lin Tsai , Kong-Beng Thei
发明人： Chen-Liang Chu , Fei-Yuh Chen , Yi-Sheng Chen , Shih-Kuang Hsiao , Chun Lin Tsai , Kong-Beng Thei
IPC分类号： H01L29/76 , H01L29/78 , H01L29/10 , H01L29/06
CPC分类号： H01L29/41775 , H01L29/0653 , H01L29/0692 , H01L29/1033 , H01L29/1045 , H01L29/78 , H01L29/7823 , H01L29/7835
摘要： A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.
摘要翻译：半导体器件包括具有通道区域的有源区域和与栅极介电层下方的沟道区域邻接的至少一个翼区域。所述至少一个机翼区域可以是穿过所述通道区域的两个对称翼区域。

9. 发明授权

US09054025B2 Process for controlling shallow trench isolation step height 有权
标题翻译：控制浅沟槽隔离台阶高度的工艺
公开(公告)号：US09054025B2
公开(公告)日：2015-06-09
申请号：US12478135
申请日：2009-06-04
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
IPC分类号： H01L21/66 , H01L21/762
CPC分类号： H01L22/20 , H01L21/76224 , H01L22/12
摘要： A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.
摘要翻译：公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

10. 发明申请

US20120270379A1 METHOD OF FABRICATING A DUMMY GATE STRUCTURE IN A GATE LAST PROCESS 有权
标题翻译：在门窗最后过程中制造多孔门结构的方法
公开(公告)号：US20120270379A1
公开(公告)日：2012-10-25
申请号：US13538220
申请日：2012-06-29
申请人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人： Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要： A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
摘要翻译：一种半导体器件制造方法，包括在衬底的第一部分中形成多个栅极结构，其中所述多个栅极结构具有第一高度。第一金属栅极结构形成在衬底的第二部分中，第一金属栅极结构被隔离区包围。在基板的第二部分中形成多个虚拟栅极结构。多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。多个虚拟结构具有与多个栅极结构基本平面的顶表面，并且覆盖基板的第二部分的图案密度的至少5％。

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