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1. 发明申请

US20060289999A1 Selective copper alloy interconnections in semiconductor devices and methods of forming the same 审中-公开
标题翻译：半导体器件中的选择性铜合金互连及其形成方法
公开(公告)号：US20060289999A1
公开(公告)日：2006-12-28
申请号：US11389868
申请日：2006-03-27
申请人： Hyo-Jong Lee , Sun-Jung Lee , Bong-Seok Suh , Hong-Jae Shin , Nae-In Lee , Kyoung-Woo Lee , Se-Young Jeong , Jeong-Hoon Ahn , Soo-Geun Lee
发明人： Hyo-Jong Lee , Sun-Jung Lee , Bong-Seok Suh , Hong-Jae Shin , Nae-In Lee , Kyoung-Woo Lee , Se-Young Jeong , Jeong-Hoon Ahn , Soo-Geun Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76807 , H01L21/76846 , H01L21/76847 , H01L21/76864 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L23/53233 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed in the dielectric. The first interconnection has a first pure copper pattern. In addition, a second interconnection having a larger width than the first interconnection is formed in the dielectric. The second interconnection has a copper alloy pattern. The copper alloy pattern may be an alloy layer formed of copper (Cu) and an additive material. A method of forming the selective copper alloy pattern is also provided.
摘要翻译：提供半导体器件中的选择性铜合金互连。互连包括衬底，形成在衬底上的电介质和形成在电介质中的第一互连。第一个互连具有第一个纯铜图案。此外，在电介质中形成具有大于第一互连的宽度的第二互连。第二互连具有铜合金图案。铜合金图案可以是由铜（Cu）和添加剂材料形成的合金层。还提供了形成选择性铜合金图案的方法。

2. 发明授权

US07417302B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07417302B2
公开(公告)日：2008-08-26
申请号：US11174864
申请日：2005-07-05
申请人： Kyoung-Woo Lee , Hong-Jae Shin , Jeong-Hoon Ahn , Seung-Man Choi , Byung-Jun Oh , Yoon-Hae Kim
发明人： Kyoung-Woo Lee , Hong-Jae Shin , Jeong-Hoon Ahn , Seung-Man Choi , Byung-Jun Oh , Yoon-Hae Kim
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L21/76808 , H01L21/76877 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.
摘要翻译：在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。沿着第一开口的内轮廓形成下电极。第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有台阶部分的第一开口。在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。在电介质层上形成上电极。因此，抑制了下电极和上电极之间的漏电流。

3. 发明申请

US20060009065A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060009065A1
公开(公告)日：2006-01-12
申请号：US11174864
申请日：2005-07-05
申请人： Kyoung-Woo Lee , Hong-Jae Shin , Jeong-Hoon Ahn , Seung-Man Choi , Byung-Jun Oh , Yoon-Hae Kim
发明人： Kyoung-Woo Lee , Hong-Jae Shin , Jeong-Hoon Ahn , Seung-Man Choi , Byung-Jun Oh , Yoon-Hae Kim
IPC分类号： H01R4/24
CPC分类号： H01L23/5223 , H01L21/76808 , H01L21/76877 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.
摘要翻译：在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。沿着第一开口的内轮廓形成下电极。第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有阶梯部分的第一开口。在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。在电介质层上形成上电极。因此，抑制了下电极和上电极之间的漏电流。

4. 发明授权

US06936533B2 Method of fabricating semiconductor devices having low dielectric interlayer insulation layer 失效
标题翻译：制造具有低介电层间绝缘层的半导体器件的方法
公开(公告)号：US06936533B2
公开(公告)日：2005-08-30
申请号：US09994508
申请日：2001-11-27
申请人： Jae-Hak Kim , Hong-Jae Shin , Soo-Geun Lee , Kyoung-Woo Lee
发明人： Jae-Hak Kim , Hong-Jae Shin , Soo-Geun Lee , Kyoung-Woo Lee
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L21/4763 , H01L21/31 , H01L23/58
CPC分类号： H01L21/76826 , H01L21/02126 , H01L21/02137 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/0234 , H01L21/02362 , H01L21/3144 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.
摘要翻译：公开了一种制造具有低介电常数的半导体器件的方法。根据该方法，形成碳氧化硅层，用等离子体处理并图案化。碳硅氧化物层通过涂布法或CVD法如PECVD法形成。用等离子体处理碳氧化硅层是通过供给至少一种选自He，H 2 H 2，N 2 O，NH 3， N 2，N 2，O 2和Ar。希望在形成硅碳化硅层之后，通过原位法将等离子体施加在PECVD器件中的碳氧化硅层。在封盖层进一步堆叠和图案化的情况下，希望用H 2 - 等离子体处理。即使在由硅碳化硅层和双镶嵌工艺的有机聚合物基团的涂层形成层间绝缘的情况下，期望在形成涂层之前进行等离子体处理。

5. 发明申请

US20060170103A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060170103A1
公开(公告)日：2006-08-03
申请号：US11344550
申请日：2006-01-30
申请人： Bong-seok Suh , Seung-man Choi , Hong-Jae Shin , Young-jin Wee
发明人： Bong-seok Suh , Seung-man Choi , Hong-Jae Shin , Young-jin Wee
IPC分类号： H01L23/52
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76864 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the amorphous metallic nitride layer, and a conductive layer filled into the opening having the diffusion barrier layer.
摘要翻译：提供了包括可靠互连的半导体器件及其制造方法。半导体器件包括衬底，具有开口的金属间电介质（IMD）图案，形成在开口的内表面上的非晶金属氮化物层，形成在非晶金属氮化物层上的扩散阻挡层，以及导电层填充到具有扩散阻挡层的开口中。

6. 发明授权

US07595253B2 Method of forming the semiconductor device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US07595253B2
公开(公告)日：2009-09-29
申请号：US11797827
申请日：2007-05-08
申请人： II-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
发明人： II-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.
摘要翻译：示例性实施例提供半导体器件及其形成方法。根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

7. 发明申请

US20070262393A1 Semiconductor devices and methods of forming the same 失效
标题翻译：半导体器件及其形成方法
公开(公告)号：US20070262393A1
公开(公告)日：2007-11-15
申请号：US11797827
申请日：2007-05-08
申请人： Il-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
发明人： Il-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
IPC分类号： H01L29/76 , H01L21/76 , H01L21/461 , H01L29/94 , H01L21/302 , H01L31/00
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.
摘要翻译：示例性实施例提供半导体器件及其形成方法。根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

8. 发明授权

US08518723B2 Method of fabricating semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US08518723B2
公开(公告)日：2013-08-27
申请号：US12591534
申请日：2009-11-23
申请人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
发明人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/0337
摘要： A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
摘要翻译：一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层来形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层他的间隔。

9. 发明申请

US20070258075A1 Apparatus for processing a semiconductor wafer and method of forming the same 审中-公开
标题翻译：用于处理半导体晶片的设备及其形成方法
公开(公告)号：US20070258075A1
公开(公告)日：2007-11-08
申请号：US11790175
申请日：2007-04-24
申请人： Ki-Chul Kim , Hong-Jae Shin , Nae-In Lee
发明人： Ki-Chul Kim , Hong-Jae Shin , Nae-In Lee
IPC分类号： G03B27/52
CPC分类号： H01L21/68721
摘要： A semiconductor wafer processing apparatus may include a chuck and/or a focus ring. The chuck may be configured to hold a wafer. The focus ring may be disposed surrounding a rim of the chuck. The focus ring may include a first section formed of a first material and a second section formed of a second material. The first material and the second material may have different conductivities. A method of forming a semiconductor wafer processing apparatus may include forming a first section of a focus ring from a first material, forming a second section of the focus ring from a second material having a different conductivity than the first material, combining the first and second sections to form a focus ring, and/or arranging the focus ring so as to surround a chuck.
摘要翻译：半导体晶片处理装置可以包括卡盘和/或聚焦环。卡盘可以被配置成保持晶片。聚焦环可以围绕卡盘的边缘设置。聚焦环可以包括由第一材料形成的第一部分和由第二材料形成的第二部分。第一材料和第二材料可以具有不同的电导率。形成半导体晶片处理装置的方法可以包括从第一材料形成聚焦环的第一部分，从具有不同于第一材料的导电率的第二材料形成聚焦环的第二部分，将第一和第二部分形成聚焦环，和/或配置聚焦环以围绕卡盘。

10. 发明申请

US20100136790A1 Method of fabricating semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20100136790A1
公开(公告)日：2010-06-03
申请号：US12591534
申请日：2009-11-23
申请人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
发明人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/0337
摘要： A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
摘要翻译：一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层他的间隔。

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