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1. 发明申请

US20060289999A1 Selective copper alloy interconnections in semiconductor devices and methods of forming the same 审中-公开
标题翻译：半导体器件中的选择性铜合金互连及其形成方法
公开(公告)号：US20060289999A1
公开(公告)日：2006-12-28
申请号：US11389868
申请日：2006-03-27
申请人： Hyo-Jong Lee , Sun-Jung Lee , Bong-Seok Suh , Hong-Jae Shin , Nae-In Lee , Kyoung-Woo Lee , Se-Young Jeong , Jeong-Hoon Ahn , Soo-Geun Lee
发明人： Hyo-Jong Lee , Sun-Jung Lee , Bong-Seok Suh , Hong-Jae Shin , Nae-In Lee , Kyoung-Woo Lee , Se-Young Jeong , Jeong-Hoon Ahn , Soo-Geun Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76807 , H01L21/76846 , H01L21/76847 , H01L21/76864 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L23/53233 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed in the dielectric. The first interconnection has a first pure copper pattern. In addition, a second interconnection having a larger width than the first interconnection is formed in the dielectric. The second interconnection has a copper alloy pattern. The copper alloy pattern may be an alloy layer formed of copper (Cu) and an additive material. A method of forming the selective copper alloy pattern is also provided.
摘要翻译：提供半导体器件中的选择性铜合金互连。互连包括衬底，形成在衬底上的电介质和形成在电介质中的第一互连。第一个互连具有第一个纯铜图案。此外，在电介质中形成具有大于第一互连的宽度的第二互连。第二互连具有铜合金图案。铜合金图案可以是由铜（Cu）和添加剂材料形成的合金层。还提供了形成选择性铜合金图案的方法。

2. 发明授权

US07560332B2 Integrated circuit capacitor structure 失效
标题翻译：集成电路电容器结构
公开(公告)号：US07560332B2
公开(公告)日：2009-07-14
申请号：US11733711
申请日：2007-04-10
申请人： Kyoung-Woo Lee , Wan-Jae Park , Jeong-Hoon Ahn , Kyung-Tae Lee , Mu-Kyeng Jung , Yong-Jun Lee , Il-Goo Kim , Soo-Geun Lee
发明人： Kyoung-Woo Lee , Wan-Jae Park , Jeong-Hoon Ahn , Kyung-Tae Lee , Mu-Kyeng Jung , Yong-Jun Lee , Il-Goo Kim , Soo-Geun Lee
IPC分类号： H01L21/8234
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.
摘要翻译：本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

3. 发明授权

US06936533B2 Method of fabricating semiconductor devices having low dielectric interlayer insulation layer 失效
标题翻译：制造具有低介电层间绝缘层的半导体器件的方法
公开(公告)号：US06936533B2
公开(公告)日：2005-08-30
申请号：US09994508
申请日：2001-11-27
申请人： Jae-Hak Kim , Hong-Jae Shin , Soo-Geun Lee , Kyoung-Woo Lee
发明人： Jae-Hak Kim , Hong-Jae Shin , Soo-Geun Lee , Kyoung-Woo Lee
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L21/4763 , H01L21/31 , H01L23/58
CPC分类号： H01L21/76826 , H01L21/02126 , H01L21/02137 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/0234 , H01L21/02362 , H01L21/3144 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.
摘要翻译：公开了一种制造具有低介电常数的半导体器件的方法。根据该方法，形成碳氧化硅层，用等离子体处理并图案化。碳硅氧化物层通过涂布法或CVD法如PECVD法形成。用等离子体处理碳氧化硅层是通过供给至少一种选自He，H 2 H 2，N 2 O，NH 3， N 2，N 2，O 2和Ar。希望在形成硅碳化硅层之后，通过原位法将等离子体施加在PECVD器件中的碳氧化硅层。在封盖层进一步堆叠和图案化的情况下，希望用H 2 - 等离子体处理。即使在由硅碳化硅层和双镶嵌工艺的有机聚合物基团的涂层形成层间绝缘的情况下，期望在形成涂层之前进行等离子体处理。

4. 发明申请

US20050088551A1 Structure of a CMOS image sensor and method for fabricating the same 有权
公开(公告)号：US20050088551A1
公开(公告)日：2005-04-28
申请号：US10973291
申请日：2004-10-27
申请人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
发明人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
IPC分类号： G01R31/28 , H01L23/532 , H01L27/146 , H01L31/0224 , H04N17/00 , H04N5/335
CPC分类号： H01L23/53238 , G01R31/2829 , H01L21/76805 , H01L27/14603 , H01L27/14623 , H01L27/14627 , H01L27/14636 , H01L27/14687 , H01L31/022408 , H01L2924/0002 , H04N17/002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

5. 发明授权

US07462507B2 Structure of a CMOS image sensor and method for fabricating the same 有权
公开(公告)号：US07462507B2
公开(公告)日：2008-12-09
申请号：US10973291
申请日：2004-10-27
申请人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
发明人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
IPC分类号： H01L21/00
CPC分类号： H01L23/53238 , G01R31/2829 , H01L21/76805 , H01L27/14603 , H01L27/14623 , H01L27/14627 , H01L27/14636 , H01L27/14687 , H01L31/022408 , H01L2924/0002 , H04N17/002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

6. 发明授权

US06855629B2 Method for forming a dual damascene wiring pattern in a semiconductor device 有权
标题翻译：在半导体器件中形成双镶嵌布线图案的方法
公开(公告)号：US06855629B2
公开(公告)日：2005-02-15
申请号：US10437529
申请日：2003-05-14
申请人： Jae-Hak Kim , Soo-Geun Lee , Wan-Jae Park , Kyoung-Woo Lee
发明人： Jae-Hak Kim , Soo-Geun Lee , Wan-Jae Park , Kyoung-Woo Lee
IPC分类号： H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808
摘要： In a method for forming a dual damascene wiring pattern, an etch stop film and an interlayer dielectric film comprising an SiOC:H group material are formed on a substrate having an electrical connection layer formed thereon. An anti-reflection layer is formed on the interlayer dielectric film. A primary opening is formed by etching the anti-reflection layer and the interlayer dielectric film to expose a surface of the etch stop film. A sacrificial film is formed comprising a low dielectric constant material in the primary opening and on the anti-reflection layer. A trench photoresist pattern having a width larger than that of the primary opening is formed on the sacrificial film after plasma-processing the sacrificial film. The sacrificial film, the anti-reflection layer and the interlayer dielectric film are sequentially etched using the trench photoresist pattern as an etch mask so as to form a secondary opening of a trench shape, and the trench photoresist pattern is removed, said secondary opening extending from an upper portion of the primary opening. The sacrificial film remaining is removed, the exposed etch stop film and anti-reflection layer are removed, the primary and secondary openings are filled with metal so as to be electrically coupled with the electrical connection layer. In this manner, damage to the etch stop layer is mitigated or eliminated during processing.
摘要翻译：在形成双镶嵌布线图案的方法中，在其上形成有电连接层的基板上形成蚀刻停止膜和包含SiOC:H基材料的层间电介质膜。在层间电介质膜上形成防反射层。通过蚀刻抗反射层和层间电介质膜形成初级开口以暴露蚀刻停止膜的表面。在初级开口和抗反射层中形成包括低介电常数材料的牺牲膜。在等离子体处理牺牲膜之后，在牺牲膜上形成具有大于初级开口的宽度的沟槽光致抗蚀剂图案。使用沟槽光致抗蚀剂图案作为蚀刻掩模，依次蚀刻牺牲膜，抗反射层和层间电介质膜，以形成沟槽形状的次级开口，并移除沟槽光致抗蚀剂图案，所述次级开口延伸从主开口的上部。去除残留的牺牲膜，去除暴露的蚀刻停止膜和抗反射层，用金属填充初级和次级开口以与电连接层电耦合。以这种方式，在处理期间减轻或消除对蚀刻停止层的损伤。

7. 发明授权

US07022600B2 Method of forming dual damascene interconnection using low-k dielectric material 有权
标题翻译：使用低k介电材料形成双镶嵌互连的方法
公开(公告)号：US07022600B2
公开(公告)日：2006-04-04
申请号：US10437806
申请日：2003-05-14
申请人： Jae-Hak Kim , Soo-Geun Lee , Ki-Kwan Park , Kyoung-Woo Lee
发明人： Jae-Hak Kim , Soo-Geun Lee , Ki-Kwan Park , Kyoung-Woo Lee
IPC分类号： H01L21/475
CPC分类号： H01L21/76811 , H01L21/76808 , H01L21/76813
摘要： In order to avoid a faulty pattern resulting from a photoresist tail being formed due to a step difference of an upper hard mask layer when a dual hard mask layer is used, a planarization layer is formed following patterning of the upper hard mask layer. In this manner, a photoresist pattern is formed without the creation of a photoresist tail. Alternatively, a single hard mask layer and a planarization layer are substituted for the dual lower hard mask layer and an upper hard mask layer, respectively. In this manner, it is therefore possible to form a photoresist pattern without a photoresist tail being formed during photolithographic processes. In order to prevent formation of a facet, the planarization layer is thickly formed or, alternatively, the hard mask layer is etched using the photoresist pattern.
摘要翻译：为了避免当使用双硬掩模层时由于上部硬掩模层的阶差而形成的光致抗蚀剂尾部产生的故障图案，在上部硬掩模层的图案化之后形成平坦化层。以这种方式，形成光致抗蚀剂图案而不产生光致抗蚀剂尾部。或者，单个硬掩模层和平坦化层分别代替双下硬掩模层和上硬掩模层。以这种方式，因此可以在光刻工艺期间形成光致抗蚀剂图案而不形成光致抗蚀剂尾部。为了防止小面的形成，平坦化层被厚地形成，或者使用光致抗蚀剂图案蚀刻硬掩模层。

8. 发明授权

US07400003B2 Structure of a CMOS image sensor and method for fabricating the same 有权
标题翻译： CMOS图像传感器的结构及其制造方法
公开(公告)号：US07400003B2
公开(公告)日：2008-07-15
申请号：US10998803
申请日：2004-11-30
申请人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
发明人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
IPC分类号： H01L31/062
CPC分类号： H01L23/53238 , G01R31/2829 , H01L21/76805 , H01L27/14603 , H01L27/14623 , H01L27/14627 , H01L27/14636 , H01L27/14687 , H01L31/022408 , H01L2924/0002 , H04N17/002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.
摘要翻译：图像传感器装置及其形成方法包括形成在基板中的光电二极管，与光电二极管电连接的至少一个电互连线，具有光入口的光通路，光通路与光电二极管对准，位于光通道的光入口之上的滤色器和位于滤光器上的透镜与光通路对准，其中至少一个电互连线包括铜互连结构，铜互连结构具有层叠形式的多个层间电介质层，相邻的层间电介质层之间的扩散阻挡层和铜互连结构与多个层间电介质层之间的阻挡金属层以及介于其间的扩散阻挡层。如果从光电二极管上方去除阻挡金属层，则图像传感器装置可以采用铜互连。

9. 发明授权

US06861686B2 Structure of a CMOS image sensor and method for fabricating the same 有权
公开(公告)号：US06861686B2
公开(公告)日：2005-03-01
申请号：US10633709
申请日：2003-08-05
申请人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
发明人： Soo-Geun Lee , Ki-Chul Park , Kyoung-Woo Lee
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L27/14 , H01L27/146 , H01L31/0224 , H04N5/335 , H04N5/369 , H04N5/374 , H01L31/062 , H01L31/113
CPC分类号： H01L31/022408 , H01L21/76801 , H01L21/76805 , H01L21/76807 , H01L21/76843 , H01L21/76844 , H01L21/76865 , H01L23/53238 , H01L27/14623 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

10. 发明授权

US06849536B2 Inter-metal dielectric patterns and method of forming the same 失效
标题翻译：金属间电介质图案及其形成方法
公开(公告)号：US06849536B2
公开(公告)日：2005-02-01
申请号：US10404210
申请日：2003-04-01
申请人： Soo-Geun Lee , Ju-Hyuk Chung , Il-Goo Kim , Kyoung-Woo Lee , Wan-Jae Park , Jae-Hak Kim
发明人： Soo-Geun Lee , Ju-Hyuk Chung , Il-Goo Kim , Kyoung-Woo Lee , Wan-Jae Park , Jae-Hak Kim
IPC分类号： H01L21/28 , H01L21/316 , H01L21/768 , H01L21/4762
CPC分类号： H01L21/76831 , H01L21/316 , H01L21/31612 , H01L21/31629 , H01L21/31633 , H01L21/31695 , H01L21/76808 , H01L21/76835 , H01L2221/1036
摘要： Provided are an inter-metal dielectric pattern and a method of forming the same. The pattern includes a lower interconnection disposed on a semiconductor substrate, a lower dielectric layer having a via hole exposing the lower interconnection and covering the semiconductor substrate where the lower interconnection is disposed, and an upper dielectric pattern and a lower capping pattern, which include a trench line exposing the via hole and sequentially stacked on the lower dielectric layer. The lower dielectric layer and the upper dielectric pattern are low k-dielectric layers formed of materials such as SiO2, SiOF, SiOC, and porous dielectric. The method includes forming an inter-metal dielectric layer including a lower dielectric layer and upper dielectric layer, which are sequentially stacked, on a lower interconnection formed on a semiconductor substrate. The inter-metal dielectric layer is patterned to form a via hole, which exposes the upper side of the lower interconnection. Then, an upper capping layer is formed on the entire surface of the semiconductor substrate including the via hole. The upper capping layer and the upper dielectric layer are successively patterned to form a trench line exposing the upper side of the via hole. The upper capping layer is formed of at least one material selected from the group consisting of a silicon oxide layer, a silicon carbide layer, a silicon nitride layer, and a silicon oxynitride layer, by using PECVD.
摘要翻译：提供了金属间介电图案及其形成方法。该图案包括布置在半导体衬底上的下部互连，具有通孔暴露下部互连并覆盖半导体衬底的下部电介质图案和下部封盖图案的下部电介质层，沟槽线暴露通孔并依次堆叠在下介电层上。下电介质层和上电介质图案是由诸如SiO 2，SiOF，SiOC和多孔电介质的材料形成的低K电介质层。该方法包括在形成在半导体衬底上的下互连件上依次层叠包括下电介质层和上电介质层的金属间电介质层。图案化金属间电介质层以形成通孔，其暴露下部互连的上侧。然后，在包括通孔的半导体衬底的整个表面上形成上覆盖层。上覆盖层和上电介质层被连续地图案化以形成暴露通孔上侧的沟槽线。通过使用PECVD，上覆盖层由选自氧化硅层，碳化硅层，氮化硅层和氮氧化硅层的至少一种材料形成。

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