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1. 发明申请

US20100136790A1 Method of fabricating semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20100136790A1
公开(公告)日：2010-06-03
申请号：US12591534
申请日：2009-11-23
申请人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
发明人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/0337
摘要： A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
摘要翻译：一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层他的间隔。

2. 发明授权

US08518723B2 Method of fabricating semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US08518723B2
公开(公告)日：2013-08-27
申请号：US12591534
申请日：2009-11-23
申请人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
发明人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/0337
摘要： A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
摘要翻译：一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层来形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层他的间隔。

3. 发明申请

US20100173497A1 Method of fabricating semiconductor integrated circuit device 审中-公开
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20100173497A1
公开(公告)日：2010-07-08
申请号：US12655837
申请日：2010-01-06
申请人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Seo-Woo Nam , In-Keun Lee , Jung-Hoon Lee
发明人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Seo-Woo Nam , In-Keun Lee , Jung-Hoon Lee
IPC分类号： H01L21/306
CPC分类号： H01L21/32139
摘要： A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each other by a first pitch and extending in a first direction; sequentially performing first etching on the second layer and the first layer using the first etch mask to form an intermediate mask pattern with second and first patterns; forming on the intermediate mask pattern a second etch mask including a plurality of second line patterns separated from each other by a second pitch and extending in a second direction other than the first direction; performing second etching using the second etch mask on a portion of the second pattern so that the remaining portion of the second pattern is left on the first pattern; performing third etching using the second etch mask under different conditions than the second etching on the first pattern and the remaining portion of second pattern of the intermediate mask pattern and forming a final mask pattern; and patterning the layer to be etched using the final mask pattern.
摘要翻译：制造半导体集成电路器件的方法包括：提供衬底; 在基板上依次形成被蚀刻层，第一层和第二层; 在所述第一层和第二层上形成第一蚀刻掩模，所述第一蚀刻掩模具有以第一间距彼此分开并沿第一方向延伸的多个第一线图案; 使用第一蚀刻掩模在第二层和第一层上顺序地执行第一蚀刻以形成具有第二和第一图案的中间掩模图案; 在所述中间掩模图案上形成第二蚀刻掩模，所述第二蚀刻掩模包括以第二间距彼此分开并沿除了所述第一方向之外的第二方向延伸的多个第二线图案; 在第二图案的一部分上使用第二蚀刻掩模进行第二蚀刻，使得第二图案的剩余部分留在第一图案上; 在与第一图案上的第二蚀刻和中间掩模图案的第二图案的剩余部分不同的条件下，使用第二蚀刻掩模进行第三蚀刻，并形成最终的掩模图案; 并使用最终的掩模图案来图案化待蚀刻的层。

4. 发明申请

US20100212833A1 Apparatus for Etching Edge of Wafer 有权
标题翻译：用于蚀刻晶片边缘的设备
公开(公告)号：US20100212833A1
公开(公告)日：2010-08-26
申请号：US12710801
申请日：2010-02-23
申请人： Chong-Kwang Chang , Oh-Sang Cho , In-Keun Lee , Hyo-Jeong Kim
发明人： Chong-Kwang Chang , Oh-Sang Cho , In-Keun Lee , Hyo-Jeong Kim
IPC分类号： H01L21/306 , H01L21/3065
CPC分类号： H01L21/67069 , H01J37/32642 , H01L21/02087
摘要： An apparatus for etching an edge of a wafer includes a chamber, a chuck disposed inside the chamber upon which the wafer is disposed, a plate spaced apart from the wafer and disposed above the wafer, and an edge ring formed along the edge of the wafer and combined with an outer periphery of the plate, wherein the edge ring comprises a ring base spaced a distance apart from the wafer to form a parallel plane with respect to the wafer, and a first ring protrusion protruding from the ring base to insulate the edge of the wafer from a central region of the wafer.
摘要翻译：用于蚀刻晶片边缘的装置包括：室，设置在其上设置晶片的室内的卡盘，与晶片间隔开并设置在晶片上方的板，以及沿着晶片边缘形成的边缘环并且与所述板的外周边结合，其中所述边缘环包括与所述晶片隔开一段距离的环形基座，以形成相对于所述晶片的平行平面;以及第一环形突起，其从所述环形基部突出以使所述边缘的晶片从晶片的中心区域。

5. 发明授权

US08349126B2 Apparatus for etching edge of wafer 有权
标题翻译：用于蚀刻晶片边缘的设备
公开(公告)号：US08349126B2
公开(公告)日：2013-01-08
申请号：US12710801
申请日：2010-02-23
申请人： Chong-Kwang Chang , Oh-Sang Cho , In-Keun Lee , Hyo-Jeong Kim
发明人： Chong-Kwang Chang , Oh-Sang Cho , In-Keun Lee , Hyo-Jeong Kim
IPC分类号： C23C16/00 , C23F1/00 , H01L21/306
CPC分类号： H01L21/67069 , H01J37/32642 , H01L21/02087
摘要： An apparatus for etching an edge of a wafer includes a chamber, a chuck disposed inside the chamber upon which the wafer is disposed, a plate spaced apart from the wafer and disposed above the wafer, and an edge ring formed along the edge of the wafer and combined with an outer periphery of the plate, wherein the edge ring comprises a ring base spaced a distance apart from the wafer to form a parallel plane with respect to the wafer, and a first ring protrusion protruding from the ring base to insulate the edge of the wafer from a central region of the wafer.
摘要翻译：用于蚀刻晶片边缘的装置包括：室，设置在其上设置晶片的室内的卡盘，与晶片间隔开并设置在晶片上方的板，以及沿着晶片边缘形成的边缘环并且与所述板的外周边结合，其中所述边缘环包括与所述晶片隔开一段距离的环形基座，以形成相对于所述晶片的平行平面;以及第一环形突起，其从所述环形基座突出以使所述边缘的晶片从晶片的中心区域。

6. 发明授权

US08357576B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08357576B2
公开(公告)日：2013-01-22
申请号：US13007096
申请日：2011-01-14
申请人： Chong-Kwang Chang , Sung-Hon Chi , Hong-Jae Shin , Yong-Jin Chung , Young-Mook Oh , Ju-Beom Yi
发明人： Chong-Kwang Chang , Sung-Hon Chi , Hong-Jae Shin , Yong-Jin Chung , Young-Mook Oh , Ju-Beom Yi
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/28079 , H01L21/28088 , H01L21/28123 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.
摘要翻译：一种制造半导体器件的方法，所述方法包括提供半导体衬底; 在所述半导体衬底上形成栅极图案，使得所述栅极图案包括栅极电介质层和牺牲栅电极; 在半导体衬底和栅极图案上形成蚀刻停止层和电介质层; 去除介电层的部分以暴露蚀刻停止层; 在所述蚀刻停止层上执行蚀刻工艺以暴露所述牺牲栅电极; 去除所述牺牲栅电极以形成沟槽; 在包括沟槽的半导体衬底上形成金属层; 去除所述金属层的部分以暴露所述介电层; 以及对所述金属层执行到预定目标的回蚀处理。

7. 发明申请

US20110256700A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20110256700A1
公开(公告)日：2011-10-20
申请号：US13087522
申请日：2011-04-15
申请人： Chong-Kwang Chang , Sung-Hon Chi , Young-Mook Oh , Ju-Beom Yi
发明人： Chong-Kwang Chang , Sung-Hon Chi , Young-Mook Oh , Ju-Beom Yi
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/82345 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： A method of fabricating a semiconductor device capable of simplifying a fabrication process is provided. The method includes providing a substrate on which first and second regions are defined, forming an interlayer insulating film including first and second trenches on the substrate, the first and second trenches being formed in the first and second regions, respectively, forming a work function adjusting metal film on an upper surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench, forming a mask film on the interlayer insulating film to fill in the first and second trenches, the mask film including a developable material, forming a mask pattern by developing the mask film, the mask pattern exposing the work function adjusting metal film formed in the first region, removing the work function adjusting metal film formed in the first region by using the mask pattern, removing the mask pattern, and forming a first metal gate in the first trench and a second metal gate in the second trench.
摘要翻译：提供了一种制造能够简化制造工艺的半导体器件的方法。该方法包括提供在其上限定了第一和第二区域的基板，在基板上形成包括第一和第二沟槽的层间绝缘膜，第一和第二沟槽分别形成在第一和第二区域中，形成功函数调整层间绝缘膜的上表面的金属膜，第一沟槽的侧表面和底表面以及第二沟槽的侧表面和底表面，在层间绝缘膜上形成掩模膜以填充第一和第二沟槽，包含可显影材料的掩模膜，通过显影掩模膜形成掩模图案，掩模图案暴露在第一区域中形成的功函数调整金属膜，通过使用掩模图案去除形成在第一区域中的功函数调节金属膜去除掩模图案，以及在第一沟槽中形成第一金属栅极和在第二沟槽中形成第二金属栅极。

8. 发明授权

US08207594B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08207594B2
公开(公告)日：2012-06-26
申请号：US12702618
申请日：2010-02-09
申请人： Dong Suk Shin , Chong-Kwang Chang
发明人： Dong Suk Shin , Chong-Kwang Chang
IPC分类号： H01L29/40
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： A semiconductor integrated circuit memory device includes a gate line that extends in a first direction, an active region adjacent to a first end of the gate line and that extends in a second direction, a silicide layer formed on a top surface of the active region, on a top surface of the gate line, on both sidewalls of the first end of the gate line, and on a transverse endwall of the first end of the gate line. A spacer may be formed on sidewalls of the gate line, excluding the first end of the gate line, and a contact shared by the active region may be formed on the first end of the gate line.
摘要翻译：半导体集成电路存储器件包括：沿第一方向延伸的栅极线，与栅极线的第一端相邻并且沿第二方向延伸的有源区，形成在有源区的顶表面上的硅化物层; 在栅极线的顶表面上，在栅极线的第一端的两个侧壁上以及在栅极线的第一端的横向端壁上。除了栅极线的第一端之外，可以在栅极线的侧壁上形成间隔物，并且可以在栅极线的第一端上形成由有源区域共享的触点。

9. 发明申请

US20100200929A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100200929A1
公开(公告)日：2010-08-12
申请号：US12702618
申请日：2010-02-09
申请人： Dong Suk Shin , Chong-Kwang Chang
发明人： Dong Suk Shin , Chong-Kwang Chang
IPC分类号： H01L29/78
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： A semiconductor integrated circuit memory device includes a gate line that extends in a first direction, an active region adjacent to a first end of the gate line and that extends in a second direction, a silicide layer formed on a top surface of the active region, on a top surface of the gate line, on both sidewalls of the first end of the gate line, and on a transverse endwall of the first end of the gate line. A spacer may be formed on sidewalls of the gate line, excluding the first end of the gate line, and a contact shared by the active region may be formed on the first end of the gate line.
摘要翻译：半导体集成电路存储器件包括：沿第一方向延伸的栅极线，与栅极线的第一端相邻并且沿第二方向延伸的有源区，形成在有源区的顶表面上的硅化物层; 在栅极线的顶表面上，在栅极线的第一端的两个侧壁上以及在栅极线的第一端的横向端壁上。除了栅极线的第一端之外，可以在栅极线的侧壁上形成间隔物，并且可以在栅极线的第一端上形成由有源区域共享的触点。

10. 发明申请

US20160293599A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160293599A1
公开(公告)日：2016-10-06
申请号：US14995457
申请日：2016-01-14
申请人： Jung-Gun You , Hyung-Jong Lee , Sung-Min Kim , Chong-Kwang Chang
发明人： Jung-Gun You , Hyung-Jong Lee , Sung-Min Kim , Chong-Kwang Chang
IPC分类号： H01L27/088 , H01L29/06 , H01L23/528
CPC分类号： H01L27/0886 , H01L23/485 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L29/0649
摘要： A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.
摘要翻译：一种半导体器件，包括由第一沟槽分隔的第一和第二鳍状图案; 与第一和第二鳍状图案相交的栅电极; 以及在所述栅极电极的至少一侧上的触点，所述触点接触所述第一鳍状图案，所述触点具有不接触所述第二鳍状图案的底表面，从所述第一沟槽的底部到最顶端的高度在第一鳍状物的第一鳍状物与第一鳍状物的第一高度相交的区域中的第一鳍状图案和从第一沟槽的底部到第二鳍状图案的最上端的高度，沿着栅极延伸的方向延伸的接触部将第二翅片图案与第二高度相交，第一高度小于第二高度。

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