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1. 发明申请

US20090057755A1 SPACER UNDERCUT FILLER, METHOD OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME 审中-公开
标题翻译：间隔底部填充器，其制造方法和包含其的制品
公开(公告)号：US20090057755A1
公开(公告)日：2009-03-05
申请号：US11845448
申请日：2007-08-27
申请人： Thomas W. Dyer , Oh-Jung Kwon , Nivo Rovedo , O Sung Kwon , Bong-Seok Suh
发明人： Thomas W. Dyer , Oh-Jung Kwon , Nivo Rovedo , O Sung Kwon , Bong-Seok Suh
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/28052 , H01L29/4933 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate; a silicide contact formed on the semiconductor substrate adjacent the gate stack, the silicide contact being in operative communication with drain and source regions formed in the semiconductor substrate; and an oxide spacer disposed between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process.
摘要翻译：本文公开了一种半导体器件，其包括形成在半导体衬底的表面上的栅极叠层; 形成在栅堆叠的每个垂直侧壁上的垂直氮化物隔离元件; 垂直氮化物间隔物的覆盖半导体衬底的部分; 形成在所述半导体衬底上的与所述栅叠层相邻的硅化物接触，所述硅化物接触与形成在所述半导体衬底中的漏极和源极区域可操作地连通; 以及设置在所述垂直氮化物间隔元件和所述硅化物接触之间的氧化物间隔物; 该氧化物间隔件用于在蚀刻过程期间最小化邻近垂直氮化物间隔物的底切。

2. 发明授权

US07335590B2 Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby 有权
标题翻译：通过选择性地形成扩散阻挡层制造半导体器件的方法和由此制造半导体器件
公开(公告)号：US07335590B2
公开(公告)日：2008-02-26
申请号：US11033189
申请日：2005-01-11
申请人： Bong-Seok Suh , Ki-Chul Park , Seung-Man Choi , Il-Ryong Kim
发明人： Bong-Seok Suh , Ki-Chul Park , Seung-Man Choi , Il-Ryong Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/2855
摘要： In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.
摘要翻译：在通过选择性地形成扩散阻挡层制造半导体器件的方法及其制造的半导体器件中，在半导体衬底上形成覆盖导电图案的导电图案和绝缘层。对绝缘层进行图案化，从而形成用于暴露导电图案的至少一部分的开口。然后，使用选择性沉积技术在具有开口的半导体衬底上形成扩散阻挡层。扩散阻挡层形成为暴露在导电图案上的厚度小于暴露在开口内部的绝缘层上的扩散阻挡层的厚度。然后，对扩散阻挡层进行蚀刻，从而形成凹陷扩散阻挡层。以这种方式，防止金属原子从填充开口的金属插塞或与绝缘层的金属互连扩散。

3. 发明授权

US07341908B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07341908B2
公开(公告)日：2008-03-11
申请号：US11344550
申请日：2006-01-30
申请人： Bong-seok Suh , Seung-man Choi , Hong-jae Shin , Young-jin Wee
发明人： Bong-seok Suh , Seung-man Choi , Hong-jae Shin , Young-jin Wee
IPC分类号： H01L21/8242
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76864 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the amorphous metallic nitride layer, and a conductive layer filled into the opening having the diffusion barrier layer.
摘要翻译：提供了包括可靠互连的半导体器件及其制造方法。半导体器件包括衬底，具有开口的金属间电介质（IMD）图案，形成在开口的内表面上的非晶金属氮化物层，形成在非晶金属氮化物层上的扩散阻挡层，以及导电层填充到具有扩散阻挡层的开口中。

4. 发明申请

US20060154465A1 Method for fabricating interconnection line in semiconductor device 审中-公开
标题翻译：在半导体器件中制造互连线的方法
公开(公告)号：US20060154465A1
公开(公告)日：2006-07-13
申请号：US11330581
申请日：2006-01-12
申请人： Bong-seok Suh , Sun-jung Lee , Hong-jae Shin , Soo-geun Lee
发明人： Bong-seok Suh , Sun-jung Lee , Hong-jae Shin , Soo-geun Lee
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76849 , H01L21/76858 , H01L21/76871 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method for fabricating an interconnection line in a semiconductor device. The method includes forming a dielectric layer pattern including a region for forming the interconnection line on a semiconductor substrate, forming a diffusion barrier layer on the dielectric layer pattern, forming a first adhesion layer on the diffusion barrier layer, forming a seed layer on the first adhesion layer, forming a conductive layer to fill the region for forming the interconnection line, performing grain growth of the conductive layer by performing a first annealing process, planarizing the conductive layer to expose the top surface of the dielectric layer pattern, and forming an interface layer through reaction between the first adhesion layer and the conductive layer by performing a second annealing process at a temperature higher than that of the first annealing process.
摘要翻译：提供一种在半导体器件中制造互连线的方法。该方法包括在半导体衬底上形成包括用于形成互连线的区域的电介质层图案，在电介质层图案上形成扩散阻挡层，在扩散阻挡层上形成第一粘附层，在第一层上形成晶种层形成导电层以填充用于形成互连线的区域，通过执行第一退火工艺来执行导电层的晶粒生长，使导电层平坦化以暴露电介质层图案的顶表面，以及形成界面通过在高于第一退火处理的温度下进行第二退火处理，在第一粘附层和导电层之间反应层。

5. 发明授权

US08633520B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08633520B2
公开(公告)日：2014-01-21
申请号：US12909002
申请日：2010-10-21
申请人： Dong-Hee Yu , Bong-Seok Suh , Yoon-Hae Kim , O Sung Kwon , Oh-Jung Kwon
发明人： Dong-Hee Yu , Bong-Seok Suh , Yoon-Hae Kim , O Sung Kwon , Oh-Jung Kwon
IPC分类号： H01L23/52
CPC分类号： H01L23/535 , H01L21/76802 , H01L21/76813 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.
摘要翻译：提供半导体器件。半导体器件包括：衬底; 在衬底中形成的器件隔离区; 在每隔两个相邻的器件隔离区域之间形成在衬底的区域中的杂质区; 形成在所述基板上的栅电极; 顺序形成在基板上的第一和第二层间绝缘膜; 形成在所述第二层间绝缘膜上并且包括金属布线层的金属层间绝缘膜; 电连接每个金属布线层和杂质区的第一接触插塞; 以及第二接触插塞，其电连接每个所述金属布线层和所述栅电极，其中所述第一接触插塞形成在所述第一和第二层间绝缘膜中，并且所述第二接触插塞形成在所述第二层间绝缘膜中。

6. 发明授权

US07863201B2 Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance 有权
标题翻译：形成具有低接触电阻的硅化源极/漏极触点的场效应晶体管的方法
公开(公告)号：US07863201B2
公开(公告)日：2011-01-04
申请号：US12402816
申请日：2009-03-12
申请人： Yong-Kuk Jeong , Bong-Seok Suh , Dong-Hee Yu , Oh-Jung Kwon , Seong-Dong Kim , O Sung Kwon
发明人： Yong-Kuk Jeong , Bong-Seok Suh , Dong-Hee Yu , Oh-Jung Kwon , Seong-Dong Kim , O Sung Kwon
IPC分类号： H01L21/31 , H01L21/469 , H01L21/00
CPC分类号： H01L29/7843 , H01L21/268 , H01L21/3105 , H01L29/6659 , H01L29/7833
摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.
摘要翻译：根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。

7. 发明授权

US07446033B2 Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
标题翻译：形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连
公开(公告)号：US07446033B2
公开(公告)日：2008-11-04
申请号：US11336905
申请日：2006-01-23
申请人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
发明人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/7684 , H01L21/76883 , Y10T428/24207
摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.
摘要翻译：使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。首先，在层间电介质层的开口中依次形成阻挡层和金属层。在金属层上进行CMP工艺以形成残留在开口内的金属互连。然后，用等离子体处理金属互连。等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。最后，形成封盖绝缘层。通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

8. 发明授权

US07332764B2 Metal-insulator-metal (MIM) capacitor and method of fabricating the same 有权
标题翻译：金属绝缘体金属（MIM）电容器及其制造方法
公开(公告)号：US07332764B2
公开(公告)日：2008-02-19
申请号：US11080567
申请日：2005-03-16
申请人： Seung-Man Choi , Ki-Chul Park , Bong-Seok Suh , Il-Ryong Kim
发明人： Seung-Man Choi , Ki-Chul Park , Bong-Seok Suh , Il-Ryong Kim
IPC分类号： H01L29/76
CPC分类号： H01L21/76841 , H01L21/76846 , H01L21/7685 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.
摘要翻译：在MIM电容器及其制造方法中，MIM电容器包括在半导体衬底上的层间绝缘层，层间绝缘层中的下部金属互连和下部金属电极，覆盖下部金属互连的金属间介电层，下金属电极和层间绝缘层，暴露下金属互连的通孔，与通孔相交的上金属互连槽，暴露下金属电极的至少一个电容器沟槽区，填充上金属互连的上金属互连金属互连槽，所述上金属互连通过所述通孔电连接到所述下金属互连，覆盖所述至少一个电容器沟槽区的内表面的电介质层和被所述电介质层包围的上金属电极以填充至少一个电容器沟槽区域。

9. 发明申请

US20060289999A1 Selective copper alloy interconnections in semiconductor devices and methods of forming the same 审中-公开
标题翻译：半导体器件中的选择性铜合金互连及其形成方法
公开(公告)号：US20060289999A1
公开(公告)日：2006-12-28
申请号：US11389868
申请日：2006-03-27
申请人： Hyo-Jong Lee , Sun-Jung Lee , Bong-Seok Suh , Hong-Jae Shin , Nae-In Lee , Kyoung-Woo Lee , Se-Young Jeong , Jeong-Hoon Ahn , Soo-Geun Lee
发明人： Hyo-Jong Lee , Sun-Jung Lee , Bong-Seok Suh , Hong-Jae Shin , Nae-In Lee , Kyoung-Woo Lee , Se-Young Jeong , Jeong-Hoon Ahn , Soo-Geun Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76807 , H01L21/76846 , H01L21/76847 , H01L21/76864 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L23/53233 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed in the dielectric. The first interconnection has a first pure copper pattern. In addition, a second interconnection having a larger width than the first interconnection is formed in the dielectric. The second interconnection has a copper alloy pattern. The copper alloy pattern may be an alloy layer formed of copper (Cu) and an additive material. A method of forming the selective copper alloy pattern is also provided.
摘要翻译：提供半导体器件中的选择性铜合金互连。互连包括衬底，形成在衬底上的电介质和形成在电介质中的第一互连。第一个互连具有第一个纯铜图案。此外，在电介质中形成具有大于第一互连的宽度的第二互连。第二互连具有铜合金图案。铜合金图案可以是由铜（Cu）和添加剂材料形成的合金层。还提供了形成选择性铜合金图案的方法。

10. 发明申请

US20060170103A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060170103A1
公开(公告)日：2006-08-03
申请号：US11344550
申请日：2006-01-30
申请人： Bong-seok Suh , Seung-man Choi , Hong-Jae Shin , Young-jin Wee
发明人： Bong-seok Suh , Seung-man Choi , Hong-Jae Shin , Young-jin Wee
IPC分类号： H01L23/52
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76864 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the amorphous metallic nitride layer, and a conductive layer filled into the opening having the diffusion barrier layer.
摘要翻译：提供了包括可靠互连的半导体器件及其制造方法。半导体器件包括衬底，具有开口的金属间电介质（IMD）图案，形成在开口的内表面上的非晶金属氮化物层，形成在非晶金属氮化物层上的扩散阻挡层，以及导电层填充到具有扩散阻挡层的开口中。

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