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1. 发明授权

US09590103B2 Semiconductor devices having multiple gate structures and methods of manufacturing such devices 有权
标题翻译：具有多个栅极结构的半导体器件和制造这种器件的方法
公开(公告)号：US09590103B2
公开(公告)日：2017-03-07
申请号：US14990863
申请日：2016-01-08
申请人： Yoon Hae Kim , Jin Wook Lee , Jong Ki Jung , Myung II Kang , Kwang Yong Yang , Kwan Heum Lee , Byeong Chan Lee
发明人： Yoon Hae Kim , Jin Wook Lee , Jong Ki Jung , Myung II Kang , Kwang Yong Yang , Kwan Heum Lee , Byeong Chan Lee
IPC分类号： H01L29/78 , H01L29/165 , H01L27/088 , H01L29/08
CPC分类号： H01L21/823431 , H01L21/308 , H01L21/31053 , H01L21/31111 , H01L21/31116 , H01L21/823418 , H01L21/823437 , H01L21/823468 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L27/1104 , H01L29/0847 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.
摘要翻译：半导体器件包括具有第一区域和第二区域的衬底，第一区域中的多个第一栅极结构，第一栅极结构彼此间隔第一距离，第二栅极结构在第二区域中形成多个第二栅极结构所述第二栅极结构彼此间隔开第二距离，所述第一栅极结构的侧壁上的第一间隔物，所述第一间隔物上的介电层，所述第二栅极结构的侧壁上的第二间隔物，间隔物在第二间隔物上。

2. 发明申请

US20110312152A1 Methods of Fabricating Integrated Circuit Devices Using Selective Etching Techniques that Account for Etching Distance Variations 审中-公开
标题翻译：使用选择性蚀刻技术制造集成电路器件的方法，其考虑蚀刻距离变化
公开(公告)号：US20110312152A1
公开(公告)日：2011-12-22
申请号：US12816649
申请日：2010-06-16
申请人： Yoon-Hae Kim , Je-Don Kim , Young-Mook Oh
发明人： Yoon-Hae Kim , Je-Don Kim , Young-Mook Oh
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/31116 , H01L27/0733 , H01L27/0805
摘要： Methods of fabricating integrated circuit devices include forming an integrated circuit capacitor on a substrate. This integrated circuit capacitor includes a lower capacitor electrode, a capacitor dielectric region on the lower capacitor electrode and an upper capacitor electrode on the capacitor dielectric region. The upper capacitor electrode has a smaller surface area relative to the lower capacitor electrode. An interlayer insulating layer is formed on the integrated circuit capacitor. This interlayer insulating layer is polished to have a planarized surface thereon that is spaced from an upper surface of the upper capacitor electrode by a first distance and spaced from an upper surface of the lower capacitor electrode by a second distance greater than the first distance. A step is performed to selectively etch first and second via holes of unequal size in the interlayer insulating layer to expose the upper surface of the lower capacitor electrode and the upper surface of the upper capacitor electrode, respectively. This etching step is performed using an etching process that concurrently etches portions of the interlayer insulating layer associated with the first via hole at a faster rate than portions of the interlayer insulating layer associated with the second via hole, which is larger than the first via hole.
摘要翻译：制造集成电路器件的方法包括在衬底上形成集成电路电容器。该集成电路电容器包括下电容器电极，下电容器电极上的电容器介电区域和电容器电介质区域上的上电容器电极。上部电容器电极相对于下部电容器电极具有较小的表面积。在集成电路电容器上形成层间绝缘层。对该层间绝缘层进行研磨，使其平坦化面与上部电容电极的上表面隔开第一距离，并与下部电容电极的上表面间隔大于第一距离的第二距离。执行步骤以选择性地蚀刻层间绝缘层中不等尺寸的第一和第二通孔，以分别暴露下电容电极的上表面和上电容器电极的上表面。该蚀刻步骤使用蚀刻工艺进行，该蚀刻工艺以比第一通孔更大的与第二通孔相关的层间绝缘层的部分更快的速率同时蚀刻与第一通孔相关联的部分的层间绝缘层，。

3. 发明授权

US07884409B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07884409B2
公开(公告)日：2011-02-08
申请号：US11760092
申请日：2007-06-08
申请人： Yoon-Hae Kim , Myoung-Hwan Oh , Myung-Soo Yeo , Hea-Yean Park
发明人： Yoon-Hae Kim , Myoung-Hwan Oh , Myung-Soo Yeo , Hea-Yean Park
IPC分类号： H01L27/108 , H01L29/94 , H01L21/02 , H01L23/52
CPC分类号： H01L28/60 , H01L21/76816
摘要： A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the first second, third and fourth conductive plates are electrically connected and constitute at least two capacitors.
摘要翻译：一种半导体器件及其制造方法，其中插入绝缘层以将半导体器件依次配置在半导体衬底上。半导体器件包括第一导电板，第二导电板，第三导电板和第四导电板。第一第二，第三和第四导电板中的至少两个电连接并构成至少两个电容器。

4. 发明申请

US20100087042A1 Methods of Fabricating Three-Dimensional Capacitor Structures Having Planar Metal-Insulator-Metal and Vertical Capacitors Therein 有权
标题翻译：制造具有平面金属 - 绝缘体 - 金属和垂直电容器的三维电容结构的方法
公开(公告)号：US20100087042A1
公开(公告)日：2010-04-08
申请号：US12246093
申请日：2008-10-06
申请人： Yoon-Hae Kim , Sun-Oo Kim
发明人： Yoon-Hae Kim , Sun-Oo Kim
IPC分类号： H01L21/02
CPC分类号： H01L21/02 , H01L23/5223 , H01L27/0688 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors.
摘要翻译：形成三维电容器网络的方法可以包括在半导体衬底上形成第一水平MIM电容器，并在第一水平MIM电容器上形成第一层间绝缘层。然后在第一层间绝缘层中形成第一垂直电容器电极，并且在第一层间绝缘层上形成第二水平MIM电容器。该第二水平MIM电容器可以通过形成上电容器电极和下电容器电极而形成。上部电容器电极可以通过第一垂直电容器电极电连接到下面的第一MIM电容器的上部电容器电极。可以形成在第一层间绝缘层中的下电容器电极可以与第一和第二MIM电容器的上电极相对延伸。

5. 发明授权

US07579643B2 Capacitor having high electrostatic capacity, integrated circuit device including the capacitor and method of fabricating the same 有权
标题翻译：具有高静电容量的电容器，包括该电容器的集成电路器件及其制造方法
公开(公告)号：US07579643B2
公开(公告)日：2009-08-25
申请号：US11706972
申请日：2007-02-16
申请人： Byung-jun Oh , Kyung-tae Lee , Yoon-hae Kim
发明人： Byung-jun Oh , Kyung-tae Lee , Yoon-hae Kim
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.
摘要翻译：电容器可以包括第一电极，第二电极，低介电层和/或高电介质层。第一电极可以包括至少一个第一电极分支。第二电极可面向第一电极并且包括至少一个第二电极分支。低电介质层可以形成在第一电极分支和第二电极分支之间。高电介质层可以形成在第一电极分支和第二电极分支之间。高介电层可以具有比低介电层更高的介电常数。

6. 发明授权

US07220652B2 Metal-insulator-metal capacitor and interconnecting structure 失效
标题翻译：金属绝缘体 - 金属电容器和互连结构
公开(公告)号：US07220652B2
公开(公告)日：2007-05-22
申请号：US10901239
申请日：2004-07-29
申请人： Yoon-hae Kim , Kyung-tae Lee , Seong-ho Liu
发明人： Yoon-hae Kim , Kyung-tae Lee , Seong-ho Liu
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L28/75
摘要： A method of manufacturing a MIM capacitor and a interconnecting structure using a damascene process. The MIM capacitor and the first interconnecting structure can be formed at equal depths.
摘要翻译：使用镶嵌工艺制造MIM电容器和互连结构的方法。 MIM电容器和第一互连结构可以以相等的深度形成。

7. 发明授权

US07202160B2 Method of forming an insulating structure having an insulating interlayer and a capping layer and method of forming a metal wiring structure using the same 失效
标题翻译：形成具有绝缘中间层和覆盖层的绝缘结构的方法和使用其形成金属布线结构的方法
公开(公告)号：US07202160B2
公开(公告)日：2007-04-10
申请号：US10899934
申请日：2004-07-27
申请人： Yoon-Hae Kim , Kyung-Tae Lee , Yong-Jun Lee
发明人： Yoon-Hae Kim , Kyung-Tae Lee , Yong-Jun Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/02126 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02362 , H01L21/3122 , H01L21/31629 , H01L21/31633 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： In a method of forming an insulating structure, an insulating interlayer is formed on a substrate using a silicon source gas and a reaction gas. A capping layer is formed in-situ on the insulating interlayer by increasing a flow rate of an oxidizing gas included in the reaction gas so that the capping layer has a second thickness when the insulating interlayer is formed on the substrate to have a first thickness. The insulating structure dose not have an interface between the insulating interlayer and the capping layer so that the insulating interlayer is not subject to damage by a cleaning solution during a subsequent cleaning process, since the cleaning solution maynot permeate into the insulating structure. Additionally, leakage current is mitigated or eliminated between the insulating interlayer and the capping layer, thereby improving the reliability of a semiconductor device including the insulating structure.
摘要翻译：在形成绝缘结构的方法中，使用硅源气体和反应气体在基板上形成绝缘中间层。通过增加反应气体中包含的氧化气体的流量，在绝缘中间层上原位形成覆盖层，使得当在基板上形成绝缘中间层以具有第一厚度时，覆盖层具有第二厚度。绝缘结构在绝缘中间层和覆盖层之间不具有界面，使得在随后的清洁过程中绝缘中间层不被清洁溶液损坏，因为清洁溶液可能不渗透到绝缘结构中。此外，在绝缘中间层和覆盖层之间减轻或消除泄漏电流，从而提高包括绝缘结构的半导体器件的可靠性。

8. 发明授权

US09754789B2 Method of fabricating semiconductor device and computing system for implementing the method 有权
公开(公告)号：US09754789B2
公开(公告)日：2017-09-05
申请号：US14509316
申请日：2014-10-08
申请人： Yoon-Hae Kim , Jong-Shik Yoon , Hwa-Sung Rhee , Byung-Sung Kim
发明人： Yoon-Hae Kim , Jong-Shik Yoon , Hwa-Sung Rhee , Byung-Sung Kim
IPC分类号： H01L21/44 , H01L21/283 , H01L21/033 , H01L21/311 , H01L21/768
CPC分类号： H01L21/283 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.

9. 发明申请

US20120193794A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120193794A1
公开(公告)日：2012-08-02
申请号：US13443442
申请日：2012-04-10
申请人： Yoon-Hae Kim , Myoung-Hwan Oh , Myung-Soo Yeo , Hea-Yean Park
发明人： Yoon-Hae Kim , Myoung-Hwan Oh , Myung-Soo Yeo , Hea-Yean Park
IPC分类号： H01L23/52
CPC分类号： H01L28/60 , H01L21/76816
摘要： A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the first, second, third and fourth conductive plates are electrically connected and constitute at least two capacitors.
摘要翻译：一种半导体器件及其制造方法，其中插入绝缘层以将半导体器件依次配置在半导体衬底上。半导体器件包括第一导电板，第二导电板，第三导电板和第四导电板。第一，第二，第三和第四导电板中的至少两个电连接并构成至少两个电容器。

10. 发明授权

US07538375B2 Capacitor structure of semiconductor device and method of fabricating the same 有权
标题翻译：半导体器件的电容器结构及其制造方法
公开(公告)号：US07538375B2
公开(公告)日：2009-05-26
申请号：US11730810
申请日：2007-04-04
申请人： Yoon-Hae Kim , Seung-Koo Lee
发明人： Yoon-Hae Kim , Seung-Koo Lee
IPC分类号： H01L27/108
CPC分类号： H01L24/03 , H01L23/5223 , H01L24/05 , H01L24/45 , H01L24/48 , H01L28/55 , H01L28/91 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01056 , H01L2924/01059 , H01L2924/01072 , H01L2924/01073 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/12036 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device having superior capacitance may include interconnections formed on a semiconductor substrate, an interlayer insulation layer on the interconnections and having vias exposing a portion of the top surface of the interconnections, a capacitor which may be on the interlayer insulation layer and having a bottom electrode, a dielectric layer pattern, and a top electrode which may be sequentially stacked, and a pad structure may be connected to the interconnections through the vias. The pad structure may include pads for bonding with external electronic devices and a first upper interconnection connected to the top electrode of the capacitor.
摘要翻译：具有优异电容的半导体器件可以包括形成在半导体衬底上的互连，互连上的层间绝缘层，并且具有暴露互连顶表面的一部分的通孔，可以在层间绝缘层上并具有底部的电容器电极，电介质层图案和可以顺序堆叠的顶部电极，并且焊盘结构可以通过通孔连接到互连。焊盘结构可以包括用于与外部电子器件接合的焊盘和连接到电容器的顶部电极的第一上部互连。

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