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    • 4. 发明授权
    • Integrated transformer and method of fabrication thereof
    • 集成变压器及其制造方法
    • US07570144B2
    • 2009-08-04
    • US11750341
    • 2007-05-18
    • Chee Chong LimKok Wai ChewKiat Seng YeoSuh Fei LimManh Anh DoLap Chan
    • Chee Chong LimKok Wai ChewKiat Seng YeoSuh Fei LimManh Anh DoLap Chan
    • H01F5/00
    • H01F17/0006H01F17/0013H01F19/08H01F27/2804H01F41/041H01L23/5227H01L2924/0002H01L2924/3011Y10T29/4902H01L2924/00
    • An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90° in a lateral direction.
    • 集成变压器结构包括与横向轴线相关联的第一线圈元件,第一线圈元件具有至少一匝。 第一线圈元件包括设置在第一横向水平面上的第一部分和设置在第二横向水平面上的第二部分。 第一和第二横向水平面沿着所述横向轴线相互间隔开。 第一和第二部分从所述轴线横向移位不同的相应距离。 所述第一线圈元件的至少一个交叉部分,其中所述第一线圈元件被配置为提供通过所述交叉部分穿过所述交叉部分的所述第一线圈元件的所述第一部分的至少一部分的导电路径,并且随后通过 第一线圈元件的第二部分的至少一部分,其中沿着所述路径的流动方向的任何变化在横向方向上小于90°。
    • 7. 发明授权
    • High performance integrated varactor on silicon
    • 硅片上高性能集成变容二极管
    • US06521939B1
    • 2003-02-18
    • US09672764
    • 2000-09-29
    • Kiat-Seng YeoChun Qi GengKok-Wai ChewManh-Anh DoJian Guo Ma
    • Kiat-Seng YeoChun Qi GengKok-Wai ChewManh-Anh DoJian Guo Ma
    • H01L27108
    • H01L29/94H01L27/0808H01L29/66181
    • A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.
    • 描述了一种新的MOS变容二极管装置。 底部电极在半导体衬底中包括多个扩散结。 半导体衬底可以是n型或p型。 扩散结被排列成二维阵列。 扩散结可以是n型或p型。 扩散结可以包含在p阱或n阱中。 电介质层覆盖在半导体衬底上。 顶部电极覆盖在电介质层上。 顶部电极包括单个多边形,其中包含其中的开口的二维阵列,其暴露扩散结。 顶部电极优选包括多晶硅。 层间电介质层覆盖上电极和扩散结。 层间电介质层具有暴露下面的扩散结的接触开口的二维阵列。 图案化金属层覆盖层间电介质层,并通过接触开口接触扩散接头。