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1. 发明授权

US08242872B2 Transformer with effective high turn ratio 有权
标题翻译：变压器有效高匝数比
公开(公告)号：US08242872B2
公开(公告)日：2012-08-14
申请号：US11779892
申请日：2007-07-19
申请人： Chee Chong Lim , Kok Wai Chew , Kiat Seng Yeo , Suh Fei Lim , Manh Anh Do , Lap Chan
发明人： Chee Chong Lim , Kok Wai Chew , Kiat Seng Yeo , Suh Fei Lim , Manh Anh Do , Lap Chan
IPC分类号： H01F5/00 , H01F27/28
CPC分类号： H01F27/2804 , H01F17/0013 , H01F27/006 , H01F2017/0073 , H01L2924/3011 , Y10T29/4902
摘要： Embodiments of the invention provide a transformer comprising: a first coil element having a transverse axis along a transverse direction, the first coil element having p turns where p is greater than or equal to 1; and a second coil element having a transverse axis generally parallel to the transverse axis of the first coil element, the second coil element having n turns, where n is greater than or equal to 5p; wherein the first and second coil elements are arranged to provide electromagnetic coupling between the coil elements along a portion of a length of the second coil element in both a transverse direction parallel to the transverse axes and a lateral direction, wherein the lateral direction is a direction normal to the transverse axes.
摘要翻译：本发明的实施例提供了一种变压器，包括：第一线圈元件，其沿着横向具有横向轴线，所述第一线圈元件具有p匝，其中p大于或等于1; 以及第二线圈元件，其具有大致平行于所述第一线圈元件的横向轴线的横轴，所述第二线圈元件具有n匝，其中n大于或等于5p; 其中所述第一和第二线圈元件布置成沿平行于横向轴线的横向方向和横向方向沿着所述第二线圈元件的长度的一部分在所述线圈元件之间提供电磁耦合，其中所述横向方向是垂直于横轴。

2. 发明申请

US20080284552A1 INTEGRATED TRANSFORMER AND METHOD OF FABRICATION THEREOF 有权
标题翻译：一体化变压器及其制造方法
公开(公告)号：US20080284552A1
公开(公告)日：2008-11-20
申请号：US11750341
申请日：2007-05-18
申请人： Chee Chong Lim , Kok Wai Chew , Kiat Seng Yeo , Suh Fei Lim , Manh Anh Do , Lap Chan
发明人： Chee Chong Lim , Kok Wai Chew , Kiat Seng Yeo , Suh Fei Lim , Manh Anh Do , Lap Chan
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F17/0013 , H01F19/08 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , Y10T29/4902 , H01L2924/00
摘要： An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90° in a lateral direction.
摘要翻译：集成变压器结构包括与横向轴线相关联的第一线圈元件，第一线圈元件具有至少一匝。第一线圈元件包括设置在第一横向水平面上的第一部分和设置在第二横向水平面上的第二部分。第一和第二横向水平面沿着所述横向轴线相互间隔开。第一和第二部分从所述轴线横向移位不同的相应距离。所述第一线圈元件的至少一个交叉部分，其中所述第一线圈元件被配置为提供通过所述交叉部分穿过所述交叉部分的所述第一线圈元件的所述第一部分的至少一部分的导电路径，并且随后通过第一线圈元件的第二部分的至少一部分，其中沿着所述路径的流动方向的任何变化在横向方向上小于90°。

3. 发明授权

US07570144B2 Integrated transformer and method of fabrication thereof 有权
标题翻译：集成变压器及其制造方法
公开(公告)号：US07570144B2
公开(公告)日：2009-08-04
申请号：US11750341
申请日：2007-05-18
申请人： Chee Chong Lim , Kok Wai Chew , Kiat Seng Yeo , Suh Fei Lim , Manh Anh Do , Lap Chan
发明人： Chee Chong Lim , Kok Wai Chew , Kiat Seng Yeo , Suh Fei Lim , Manh Anh Do , Lap Chan
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F17/0013 , H01F19/08 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , Y10T29/4902 , H01L2924/00
摘要： An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90° in a lateral direction.
摘要翻译：集成变压器结构包括与横向轴线相关联的第一线圈元件，第一线圈元件具有至少一匝。第一线圈元件包括设置在第一横向水平面上的第一部分和设置在第二横向水平面上的第二部分。第一和第二横向水平面沿着所述横向轴线相互间隔开。第一和第二部分从所述轴线横向移位不同的相应距离。所述第一线圈元件的至少一个交叉部分，其中所述第一线圈元件被配置为提供通过所述交叉部分穿过所述交叉部分的所述第一线圈元件的所述第一部分的至少一部分的导电路径，并且随后通过第一线圈元件的第二部分的至少一部分，其中沿着所述路径的流动方向的任何变化在横向方向上小于90°。

4. 发明授权

US08237531B2 Tunable high quality factor inductor 有权
标题翻译：可调高品质因数电感
公开(公告)号：US08237531B2
公开(公告)日：2012-08-07
申请号：US11967270
申请日：2007-12-31
申请人： Ping Qiu , Chirn Chye Boon , Johnny Kok Wai Chew , Kiat Seng Yeo , Manh Anh Do , Lap Chan , Suh Fei Lim
发明人： Ping Qiu , Chirn Chye Boon , Johnny Kok Wai Chew , Kiat Seng Yeo , Manh Anh Do , Lap Chan , Suh Fei Lim
IPC分类号： H01F5/00 , H01F27/28 , H03J3/00
CPC分类号： H03J3/20 , H01F17/0006 , H01F2017/0073 , H03H11/48
摘要： An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.
摘要翻译：具有高质量（Q）因子的电感器电路包括初级电感器和补偿子电路。补偿子电路与主电感器电隔离。补偿子电路与初级电感器磁耦合，以补偿初级电感器的损耗。

5. 发明授权

US06221727B1 Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology 有权
标题翻译：在硅基板上捕获空气的方法，以改善CMOS技术中RF电感器的品质因素
公开(公告)号：US06221727B1
公开(公告)日：2001-04-24
申请号：US09385524
申请日：1999-08-30
申请人： Lap Chan , Johnny Kok Wai Chew , Cher Liang Cha , Chee Tee Chua
发明人： Lap Chan , Johnny Kok Wai Chew , Cher Liang Cha , Chee Tee Chua
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01L21/764 , H01L27/08
摘要： A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is deposited over the substrate and within the well. The polish stop layer is covered and the well filled with a spin-on-glass layer. The spin-on-glass layer is polished back to the polish stop layer. The said polish stop layer is removed. A first oxide layer is deposited overlying the spin-on-glass layer and the semiconductor substrate and is patterned using an inductor reticle whereby a plurality of openings are made through the first oxide layer to the spin-on-glass layer. All of the spin-on-glass layer within the well is removed through the plurality of openings. Thereafter, a second oxide layer is deposited overlying the first oxide layer and capping the plurality of openings thereby forming an air barrier within the well. A metal layer is deposited overlying the second oxide layer and patterned using the same inductor reticle to form the inductor in the fabrication of an integrated circuit device.
摘要翻译：描述了在制造集成电路中制造利用空气作为下层屏障的电感器的新方法。在半导体衬底中形成场氧化物区域，然后去除，从而在半导体衬底中留下阱。抛光停止层沉积在基底上并在孔内。抛光停止层被覆盖并充满了旋涂玻璃层。旋涂玻璃层被抛光回抛光停止层。所述抛光停止层被去除。沉积在旋涂玻璃层和半导体衬底上的第一氧化物层，并且使用电感器掩模版进行图案化，由此通过第一氧化物层到旋涂玻璃层制成多个开口。孔内的所有旋涂玻璃层通过多个开口被去除。此后，将第二氧化物层沉积在第一氧化物层上并覆盖多个开口，从而在该阱内形成空气屏障。沉积在第二氧化物层上的金属层，并使用相同的电感器掩模版进行图案化以在集成电路器件的制造中形成电感器。

6. 发明授权

US09262732B2 System and method of enterprise action item planning, executing, tracking and analytics 有权
标题翻译：企业行动项目计划，执行，跟踪和分析的系统和方法
公开(公告)号：US09262732B2
公开(公告)日：2016-02-16
申请号：US13166501
申请日：2011-06-22
申请人： Bin Duan , Lap Chan
发明人： Bin Duan , Lap Chan
IPC分类号： G06Q10/06 , H04W64/00
CPC分类号： G06Q10/0631 , H04W64/006
摘要： A system and method of tracking action items in an enterprise data processing environment. The method includes receiving, by a client from a server, an action item that includes a location. The method further includes performing a check-in, by the client, at the location related to the action item. The method further includes performing a check-out, by the client, related to the action item. The method further includes changing, by the client, the status of the action item. In this manner, a database of action items and statuses may be developed for more effective business collaboration and business management.
摘要翻译：跟踪企业数据处理环境中的动作项目的系统和方法。该方法包括由客户端从服务器接收包括位置的动作项目。该方法还包括由客户端在与该动作项目相关的位置处执行登记。该方法还包括由客户端执行与该动作项目相关的退房。该方法还包括由客户端改变动作项目的状态。以这种方式，可以开发一个行动项目和状态的数据库，用于更有效的业务协作和业务管理。

7. 发明申请

US20140123068A1 Content Management Systems and Methods 有权
标题翻译：内容管理系统与方法
公开(公告)号：US20140123068A1
公开(公告)日：2014-05-01
申请号：US13661687
申请日：2012-10-26
申请人： Lap Chan
发明人： Lap Chan
IPC分类号： G06F3/048
CPC分类号： G06F3/04817 , G06F3/0482 , G06F3/0486 , G06F3/04886 , H04M1/72519
摘要： Example systems and methods of managing content are described. In one implementation, a method accesses a first set of data, if second set of data, and menu data. The menu data is associated with multiple menu actions relevant to the first set of data and the second set of data. The method generates display data that allows a display device to present the first set of data, the second set of data, and the menu to a user such that the menu is positioned between the first set of data and the second set of data. The method receives a user selection of a menu action and, based on the user selection, generates a graphical object that allows the user to indicate whether to apply the selected menu action to the first set of data or the second set of data.
摘要翻译：描述了管理内容的示例系统和方法。在一个实现中，一种方法访问第一组数据，如果是第二组数据，则菜单数据。菜单数据与与第一组数据和第二组数据相关的多个菜单操作相关联。该方法产生允许显示设备向用户呈现第一组数据，第二组数据和菜单的显示数据，使得菜单位于第一组数据和第二组数据之间。该方法接收菜单动作的用户选择，并且基于用户选择，生成允许用户指示是否将所选择的菜单动作应用于第一组数据或第二组数据的图形对象。

8. 发明授权

US07932152B2 Method of forming a gate stack structure 有权
标题翻译：形成栅极堆叠结构的方法
公开(公告)号：US07932152B2
公开(公告)日：2011-04-26
申请号：US12025789
申请日：2008-02-05
申请人： Will Wong , Lap Chan , Alan Lek
发明人： Will Wong , Lap Chan , Alan Lek
IPC分类号： H01L21/8234
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/823462 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.
摘要翻译：一种在基板上形成集成电路结构的方法，所述基板包括主区域和次区域。在衬底上形成第一厚度的第一材料的第一层。第一层的一部分在主区域上被去除以暴露衬底。该结构暴露于氧化介质。这形成例如基板的氧化物材料主区域的第二层。第二层具有第二厚度。另外，所述第一层的至少一部分被转换成例如氮氧化物材料的第三层。第三层具有第三厚度。

9. 发明申请

US20050196931A1 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US20050196931A1
公开(公告)日：2005-09-08
申请号：US11123748
申请日：2005-05-04
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

10. 发明申请

US20050156269A1 Method and apparatus for performing nickel salicidation 有权
公开(公告)号：US20050156269A1
公开(公告)日：2005-07-21
申请号：US11081908
申请日：2005-03-15
申请人： Pooi Lee , Kin Pey , Alex See , Lap Chan
发明人： Pooi Lee , Kin Pey , Alex See , Lap Chan
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/49 , H01L27/095
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/4933
摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

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