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1. 发明授权

US09262732B2 System and method of enterprise action item planning, executing, tracking and analytics 有权
标题翻译：企业行动项目计划，执行，跟踪和分析的系统和方法
公开(公告)号：US09262732B2
公开(公告)日：2016-02-16
申请号：US13166501
申请日：2011-06-22
申请人： Bin Duan , Lap Chan
发明人： Bin Duan , Lap Chan
IPC分类号： G06Q10/06 , H04W64/00
CPC分类号： G06Q10/0631 , H04W64/006
摘要： A system and method of tracking action items in an enterprise data processing environment. The method includes receiving, by a client from a server, an action item that includes a location. The method further includes performing a check-in, by the client, at the location related to the action item. The method further includes performing a check-out, by the client, related to the action item. The method further includes changing, by the client, the status of the action item. In this manner, a database of action items and statuses may be developed for more effective business collaboration and business management.
摘要翻译：跟踪企业数据处理环境中的动作项目的系统和方法。该方法包括由客户端从服务器接收包括位置的动作项目。该方法还包括由客户端在与该动作项目相关的位置处执行登记。该方法还包括由客户端执行与该动作项目相关的退房。该方法还包括由客户端改变动作项目的状态。以这种方式，可以开发一个行动项目和状态的数据库，用于更有效的业务协作和业务管理。

2. 发明申请

US20140123068A1 Content Management Systems and Methods 有权
标题翻译：内容管理系统与方法
公开(公告)号：US20140123068A1
公开(公告)日：2014-05-01
申请号：US13661687
申请日：2012-10-26
申请人： Lap Chan
发明人： Lap Chan
IPC分类号： G06F3/048
CPC分类号： G06F3/04817 , G06F3/0482 , G06F3/0486 , G06F3/04886 , H04M1/72519
摘要： Example systems and methods of managing content are described. In one implementation, a method accesses a first set of data, if second set of data, and menu data. The menu data is associated with multiple menu actions relevant to the first set of data and the second set of data. The method generates display data that allows a display device to present the first set of data, the second set of data, and the menu to a user such that the menu is positioned between the first set of data and the second set of data. The method receives a user selection of a menu action and, based on the user selection, generates a graphical object that allows the user to indicate whether to apply the selected menu action to the first set of data or the second set of data.
摘要翻译：描述了管理内容的示例系统和方法。在一个实现中，一种方法访问第一组数据，如果是第二组数据，则菜单数据。菜单数据与与第一组数据和第二组数据相关的多个菜单操作相关联。该方法产生允许显示设备向用户呈现第一组数据，第二组数据和菜单的显示数据，使得菜单位于第一组数据和第二组数据之间。该方法接收菜单动作的用户选择，并且基于用户选择，生成允许用户指示是否将所选择的菜单动作应用于第一组数据或第二组数据的图形对象。

3. 发明授权

US07932152B2 Method of forming a gate stack structure 有权
标题翻译：形成栅极堆叠结构的方法
公开(公告)号：US07932152B2
公开(公告)日：2011-04-26
申请号：US12025789
申请日：2008-02-05
申请人： Will Wong , Lap Chan , Alan Lek
发明人： Will Wong , Lap Chan , Alan Lek
IPC分类号： H01L21/8234
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/823462 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.
摘要翻译：一种在基板上形成集成电路结构的方法，所述基板包括主区域和次区域。在衬底上形成第一厚度的第一材料的第一层。第一层的一部分在主区域上被去除以暴露衬底。该结构暴露于氧化介质。这形成例如基板的氧化物材料主区域的第二层。第二层具有第二厚度。另外，所述第一层的至少一部分被转换成例如氮氧化物材料的第三层。第三层具有第三厚度。

4. 发明申请

US20090167466A1 TUNABLE HIGH QUALITY FACTOR INDUCTOR 有权
标题翻译：可靠的高品质因子电感
公开(公告)号：US20090167466A1
公开(公告)日：2009-07-02
申请号：US11967270
申请日：2007-12-31
申请人： Ping QIU , Chirn Chye BOON , Johnny Kok Wai CHEW , Kiat Seng YEO , Manh Anh DO , Lap CHAN , Suh Fei LIM
发明人： Ping QIU , Chirn Chye BOON , Johnny Kok Wai CHEW , Kiat Seng YEO , Manh Anh DO , Lap CHAN , Suh Fei LIM
IPC分类号： H03J3/00 , H01F27/06
CPC分类号： H03J3/20 , H01F17/0006 , H01F2017/0073 , H03H11/48
摘要： An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.
摘要翻译：具有高质量（Q）因子的电感器电路包括初级电感器和补偿子电路。补偿子电路与主电感器电隔离。补偿子电路与初级电感器磁耦合，以补偿初级电感器的损耗。

5. 发明申请

US20050196931A1 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US20050196931A1
公开(公告)日：2005-09-08
申请号：US11123748
申请日：2005-05-04
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

6. 发明申请

US20050156269A1 Method and apparatus for performing nickel salicidation 有权
公开(公告)号：US20050156269A1
公开(公告)日：2005-07-21
申请号：US11081908
申请日：2005-03-15
申请人： Pooi Lee , Kin Pey , Alex See , Lap Chan
发明人： Pooi Lee , Kin Pey , Alex See , Lap Chan
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/49 , H01L27/095
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/4933
摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

7. 发明申请

US20050145953A1 Heterojunction BiCMOS integrated circuits and method therefor 审中-公开
标题翻译：异质结BiCMOS集成电路及其方法
公开(公告)号：US20050145953A1
公开(公告)日：2005-07-07
申请号：US10752454
申请日：2004-01-05
申请人： Lap Chan , Jia Zheng , Purakh Verma , Jian Li , Shao-fu Chu
发明人： Lap Chan , Jia Zheng , Purakh Verma , Jian Li , Shao-fu Chu
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L31/113
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623
摘要： A method of manufacturing a BiCMOS integrated circuit including a CMOS transistor having a gate structure, and a heterojunction bipolar transistor having an extrinsic base structure. A substrate is provided, and a polysilicon layer is formed over the substrate. The gate structure and the extrinsic base structure are formed in the polysilicon layer. A plurality of contacts is formed through the interlevel dielectric layer to the CMOS transistor and the heterojunction bipolar transistor.
摘要翻译：一种制造包括具有栅极结构的CMOS晶体管的BiCMOS集成电路的方法和具有外在基极结构的异质结双极晶体管。提供衬底，并且在衬底上形成多晶硅层。栅极结构和非本征基极结构形成在多晶硅层中。多个触点通过层间介质层形成到CMOS晶体管和异质结双极晶体管。

8. 发明申请

US20050101096A1 SELF-ALIGNED LATERAL HETEROJUNCTION BIPOLAR TRANSISTOR 有权
标题翻译：自对准侧向异相双极晶体管
公开(公告)号：US20050101096A1
公开(公告)日：2005-05-12
申请号：US10703284
申请日：2003-11-06
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-Fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-Fu Chu
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

9. 发明申请

US20050009357A1 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
标题翻译：通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程
公开(公告)号：US20050009357A1
公开(公告)日：2005-01-13
申请号：US10909523
申请日：2004-08-02
申请人： Lap Chan , Sanford Chu , Chit Ng , Purakh Verma , Jia Zheng , Johnny Chew , Choon Sia
发明人： Lap Chan , Sanford Chu , Chit Ng , Purakh Verma , Jia Zheng , Johnny Chew , Choon Sia
IPC分类号： H01L21/20 , H01L21/265 , H01L21/302 , H01L21/461 , H01L21/764
CPC分类号： H01L21/764 , H01L21/26506
摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.
摘要翻译：降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。在所述至少一个上介电层上形成钝化层。图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

10. 发明授权

US06680239B1 Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant 失效
标题翻译：有效的隔离与高纵横比浅沟槽隔离和氧或野外植入
公开(公告)号：US06680239B1
公开(公告)日：2004-01-20
申请号：US09624025
申请日：2000-07-24
申请人： Cher Liang Cha , Kok Keng Ong , Alex See , Lap Chan
发明人： Cher Liang Cha , Kok Keng Ong , Alex See , Lap Chan
IPC分类号： H01L2176
CPC分类号： H01L21/76237
摘要： A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench. This method is achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.
摘要翻译：给出了一种形成具有较高纵横比的浅沟槽隔离（STI）的方法。该方法允许形成更窄和更深的沟槽隔离区域，同时避免由于过度蚀刻和严重的微负载效应引起的基板损伤。此外，它产生均匀的深度沟槽，同时避免沟槽底部的蚀刻残留问题。该方法通过使用其中蚀刻沟槽的工艺和沿着沟槽的底部和侧壁生长的氧化物层来实现。然后将氧或场隔离离子注入到沟槽的底部。然后沿着沟槽的底部和侧壁形成氮化物间隔物，随后通过各向同性蚀刻从沟槽的底部去除氮化物和氧化物。氧化物沉积然后填充沟槽，随后是完成隔离结构的平坦化步骤。

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