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1. 发明申请

US20120007214A1 INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有分层电容器的集成电路系统及其制造方法
公开(公告)号：US20120007214A1
公开(公告)日：2012-01-12
申请号：US13236295
申请日：2011-09-19
申请人： Shao-fu Sanford Chu , Shaoqiang Zhang , Johnny Kok Wai Chew
发明人： Shao-fu Sanford Chu , Shaoqiang Zhang , Johnny Kok Wai Chew
IPC分类号： H01L29/92 , H01L21/20
CPC分类号： H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.
摘要翻译：一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且互连所述第一组金属层，包括互连与第二簇相邻的第一簇，以形成电容器。

2. 发明授权

US06221727B1 Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology 有权
标题翻译：在硅基板上捕获空气的方法，以改善CMOS技术中RF电感器的品质因素
公开(公告)号：US06221727B1
公开(公告)日：2001-04-24
申请号：US09385524
申请日：1999-08-30
申请人： Lap Chan , Johnny Kok Wai Chew , Cher Liang Cha , Chee Tee Chua
发明人： Lap Chan , Johnny Kok Wai Chew , Cher Liang Cha , Chee Tee Chua
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01L21/764 , H01L27/08
摘要： A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is deposited over the substrate and within the well. The polish stop layer is covered and the well filled with a spin-on-glass layer. The spin-on-glass layer is polished back to the polish stop layer. The said polish stop layer is removed. A first oxide layer is deposited overlying the spin-on-glass layer and the semiconductor substrate and is patterned using an inductor reticle whereby a plurality of openings are made through the first oxide layer to the spin-on-glass layer. All of the spin-on-glass layer within the well is removed through the plurality of openings. Thereafter, a second oxide layer is deposited overlying the first oxide layer and capping the plurality of openings thereby forming an air barrier within the well. A metal layer is deposited overlying the second oxide layer and patterned using the same inductor reticle to form the inductor in the fabrication of an integrated circuit device.
摘要翻译：描述了在制造集成电路中制造利用空气作为下层屏障的电感器的新方法。在半导体衬底中形成场氧化物区域，然后去除，从而在半导体衬底中留下阱。抛光停止层沉积在基底上并在孔内。抛光停止层被覆盖并充满了旋涂玻璃层。旋涂玻璃层被抛光回抛光停止层。所述抛光停止层被去除。沉积在旋涂玻璃层和半导体衬底上的第一氧化物层，并且使用电感器掩模版进行图案化，由此通过第一氧化物层到旋涂玻璃层制成多个开口。孔内的所有旋涂玻璃层通过多个开口被去除。此后，将第二氧化物层沉积在第一氧化物层上并覆盖多个开口，从而在该阱内形成空气屏障。沉积在第二氧化物层上的金属层，并使用相同的电感器掩模版进行图案化以在集成电路器件的制造中形成电感器。

3. 发明授权

US08536016B2 Integrated circuit system with hierarchical capacitor and method of manufacture thereof 有权
标题翻译：具有分层电容器的集成电路系统及其制造方法
公开(公告)号：US08536016B2
公开(公告)日：2013-09-17
申请号：US13236295
申请日：2011-09-19
申请人： Shao-fu Sanford Chu , Shaoqiang Zhang , Johnny Kok Wai Chew
发明人： Shao-fu Sanford Chu , Shaoqiang Zhang , Johnny Kok Wai Chew
IPC分类号： H01L21/20
CPC分类号： H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.
摘要翻译：一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且互连所述第一组金属层，包括互连与第二簇相邻的第一簇，以形成电容器。

4. 发明申请

US20090167466A1 TUNABLE HIGH QUALITY FACTOR INDUCTOR 有权
标题翻译：可靠的高品质因子电感
公开(公告)号：US20090167466A1
公开(公告)日：2009-07-02
申请号：US11967270
申请日：2007-12-31
申请人： Ping QIU , Chirn Chye BOON , Johnny Kok Wai CHEW , Kiat Seng YEO , Manh Anh DO , Lap CHAN , Suh Fei LIM
发明人： Ping QIU , Chirn Chye BOON , Johnny Kok Wai CHEW , Kiat Seng YEO , Manh Anh DO , Lap CHAN , Suh Fei LIM
IPC分类号： H03J3/00 , H01F27/06
CPC分类号： H03J3/20 , H01F17/0006 , H01F2017/0073 , H03H11/48
摘要： An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.
摘要翻译：具有高质量（Q）因子的电感器电路包括初级电感器和补偿子电路。补偿子电路与主电感器电隔离。补偿子电路与初级电感器磁耦合，以补偿初级电感器的损耗。

5. 发明授权

US06709918B1 Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology 有权
标题翻译：用于铜后端（BEOL）技术的金属绝缘体金属（MIM）电容器和金属电阻器的制造方法
公开(公告)号：US06709918B1
公开(公告)日：2004-03-23
申请号：US10307674
申请日：2002-12-02
申请人： Chit Hwei Ng , Jian Xun Li , Kok Wai Chew , Tjin Tjin Tjoa , Chaw Sing Ho , Shao Fu Sanford Chu
发明人： Chit Hwei Ng , Jian Xun Li , Kok Wai Chew , Tjin Tjin Tjoa , Chaw Sing Ho , Shao Fu Sanford Chu
IPC分类号： H01L218242
CPC分类号： H01L28/20 , H01L23/5223 , H01L23/5228 , H01L28/40 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： A method for making concurrently metal-insulator-metal (MIM) capacitors and a metal resistors in a Cu damascene back-end-of-line process is achieved. The method forms a Cu capacitor bottom metal plate using a dual-damascene process. A Si3N4 or SiC is deposited to form a capacitor dielectric layer on the Cu bottom plate. A metal layer having an upper etch-stop layer is deposited and patterned to form concurrently capacitor top plates and metal resistors. The patterning is terminated in the capacitor dielectric layer to prevent Cu particle contamination. An insulating layer is deposited and via holes are etched to the capacitor top plates and the metal resistors using the upper etch-stop layer to prevent overetching and damage. The method provides a MIM capacitor using only one additional photoresist mask while improving process yield.
摘要翻译：实现了一种在金铜绝缘体金属（MIM）电容器和金属电阻器Cu铜镶嵌后端工艺中的制造方法。该方法使用双镶嵌工艺形成Cu电容器底部金属板。沉积Si 3 N 4或SiC以在Cu底板上形成电容器电介质层。具有上蚀刻停止层的金属层被沉积并图案化以形成电容器顶板和金属电阻器。图案化终止在电容器电介质层中以防止Cu颗粒污染。沉积绝缘层，并且使用上蚀刻停止层将电容器顶板和金属电阻器的通孔蚀刻以防止过蚀刻和损坏。该方法提供了仅使用一种附加光致抗蚀剂掩模的MIM电容器，同时提高了工艺产量。

6. 发明授权

US08643461B2 Integrated transformer 有权
标题翻译：集成变压器
公开(公告)号：US08643461B2
公开(公告)日：2014-02-04
申请号：US13095932
申请日：2011-04-28
申请人： Chee Chong Lim , Johnny Kok Wai Chew , Suh Fei Lim , Wei Gao
发明人： Chee Chong Lim , Johnny Kok Wai Chew , Suh Fei Lim , Wei Gao
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01F19/04 , H01F2027/2809 , H01L2924/0002 , H01L2924/00
摘要： A device having a substrate and a dielectric layer disposed over the substrate is disclosed. The device includes a transformer layout disposed in the dielectric layer. The transformer layout includes an integrated transformer having primary and secondary coil elements. The first and second coil elements are configured to result in noise-self cancellation effect.
摘要翻译：公开了一种具有衬底和设置在衬底上的电介质层的器件。该装置包括布置在电介质层中的变压器布局。变压器布局包括具有初级和次级线圈元件的集成变压器。第一和第二线圈元件被配置成导致噪声自消除效应。

7. 发明申请

US20120274434A1 INTEGRATED TRANSFORMER 有权
标题翻译：集成变压器
公开(公告)号：US20120274434A1
公开(公告)日：2012-11-01
申请号：US13095932
申请日：2011-04-28
申请人： Chee Chong LIM , Johnny Kok Wai CHEW , Suh Fei LIM , Wei GAO
发明人： Chee Chong LIM , Johnny Kok Wai CHEW , Suh Fei LIM , Wei GAO
IPC分类号： H01F5/00 , H01F41/04
CPC分类号： H01L23/5227 , H01F19/04 , H01F2027/2809 , H01L2924/0002 , H01L2924/00
摘要： A device having a substrate and a dielectric layer disposed over the substrate is disclosed. The device includes a transformer layout disposed in the dielectric layer. The transformer layout includes an integrated transformer having primary and secondary coil elements. The first and second coil elements are configured to result in noise-self cancellation effect.
摘要翻译：公开了一种具有衬底和设置在衬底上的电介质层的器件。该装置包括布置在电介质层中的变压器布局。变压器布局包括具有初级和次级线圈元件的集成变压器。第一和第二线圈元件被配置成导致噪声自消除效应。

8. 发明授权

US08242872B2 Transformer with effective high turn ratio 有权
标题翻译：变压器有效高匝数比
公开(公告)号：US08242872B2
公开(公告)日：2012-08-14
申请号：US11779892
申请日：2007-07-19
申请人： Chee Chong Lim , Kok Wai Chew , Kiat Seng Yeo , Suh Fei Lim , Manh Anh Do , Lap Chan
发明人： Chee Chong Lim , Kok Wai Chew , Kiat Seng Yeo , Suh Fei Lim , Manh Anh Do , Lap Chan
IPC分类号： H01F5/00 , H01F27/28
CPC分类号： H01F27/2804 , H01F17/0013 , H01F27/006 , H01F2017/0073 , H01L2924/3011 , Y10T29/4902
摘要： Embodiments of the invention provide a transformer comprising: a first coil element having a transverse axis along a transverse direction, the first coil element having p turns where p is greater than or equal to 1; and a second coil element having a transverse axis generally parallel to the transverse axis of the first coil element, the second coil element having n turns, where n is greater than or equal to 5p; wherein the first and second coil elements are arranged to provide electromagnetic coupling between the coil elements along a portion of a length of the second coil element in both a transverse direction parallel to the transverse axes and a lateral direction, wherein the lateral direction is a direction normal to the transverse axes.
摘要翻译：本发明的实施例提供了一种变压器，包括：第一线圈元件，其沿着横向具有横向轴线，所述第一线圈元件具有p匝，其中p大于或等于1; 以及第二线圈元件，其具有大致平行于所述第一线圈元件的横向轴线的横轴，所述第二线圈元件具有n匝，其中n大于或等于5p; 其中所述第一和第二线圈元件布置成沿平行于横向轴线的横向方向和横向方向沿着所述第二线圈元件的长度的一部分在所述线圈元件之间提供电磁耦合，其中所述横向方向是垂直于横轴。

9. 发明授权

US08021954B2 Integrated circuit system with hierarchical capacitor and method of manufacture thereof 有权
标题翻译：具有层状电容器的集成电路系统及其制造方法
公开(公告)号：US08021954B2
公开(公告)日：2011-09-20
申请号：US12471007
申请日：2009-05-22
申请人： Shao-fu Sanford Chu , Shaoqing Zhang , Johnny Kok Wai Chew , Chit Hwei Ng
发明人： Shao-fu Sanford Chu , Shaoqing Zhang , Johnny Kok Wai Chew , Chit Hwei Ng
IPC分类号： H01L21/20 , H01L21/02
CPC分类号： H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.
摘要翻译：一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且将所述第一组金属层与所述第二组金属层互连以形成电容器。

10. 发明授权

US07721414B2 Method of manufacturing 3-D spiral stacked inductor on semiconductor material 有权
标题翻译：在半导体材料上制造三维螺旋堆叠电感器的方法
公开(公告)号：US07721414B2
公开(公告)日：2010-05-25
申请号：US10962007
申请日：2004-10-08
申请人： Choon-Beng Sia , Kiat Seng Yeo , Shao-fu Sanford Chu , Cheng Yeow Ng , Kok Wai Chew , Wang Ling Goh
发明人： Choon-Beng Sia , Kiat Seng Yeo , Shao-fu Sanford Chu , Cheng Yeow Ng , Kok Wai Chew , Wang Ling Goh
IPC分类号： H01F7/06 , H01F3/00
CPC分类号： H01L28/10 , H01L27/08 , Y10T29/4902 , Y10T29/4906 , Y10T29/49073 , Y10T29/49165
摘要： A method of manufacturing a 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and a dielectric material contains the first and second connecting portions and the plurality of turns over the substrate.
摘要翻译：提供了一种制造3-D螺旋堆叠电感器的方法，其具有多个电平的多个匝数的基板，其中电平的数量从电感器的内部匝数增加到外部匝数。第一连接部分和第二连接部分分别连接到内匝和最外匝，电介质材料包含基片上的第一和第二连接部分和多个匝。

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