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    • 1. 发明申请
    • REFERENCE FOR CMOS MEMORY CELL HAVING PMOS AND NMOS TRANSISTORS WITH A COMMON FLOATING GATE
    • 具有通用浮动栅的PMOS和NMOS晶体管的CMOS存储单元的参考
    • WO1996033496A1
    • 1996-10-24
    • PCT/US1996004124
    • 1996-03-26
    • ADVANCED MICRO DEVICES, INC.
    • ADVANCED MICRO DEVICES, INC.SHARPE-GEISLER, Bradley, A.
    • G11C05/14
    • G11C5/147G05F3/247
    • A voltage reference for a CMOS memory cell having PMOS and NMOS transistors with a common floating gate. The reference provides a more stable voltage than voltage supplied from the Vcc pin of a chip. In one embodiment, the reference includes PMOS and NMOS transistors with a common floating gate connected to their drains. A weak current source supplies current to the source of the PMOS transistor of the reference so that voltage at the source of the PMOS transistor of the reference equals the magnitude of the sum of threshold voltages (Vtn + Vtp) of the NMOS and PMOS transistors of the reference. The voltage at the source of the PMOS transistor of the reference is provided as a reference to the source of the PMOS transistor of the CMOS memory cell. To assure zero power operation in subsequent cells following CMOS memory cells utilizing such a reference, cell implants are utilized in the CMOS memory cells and the reference to assure Vtn + Vtp is greater than or equal Vcc, and voltage to the reference is boosted above Vcc.
    • 具有具有公共浮动栅极的PMOS和NMOS晶体管的CMOS存储单元的参考电压。 该参考电压提供比由芯片的Vcc引脚提供的电压更稳定的电压。 在一个实施例中,该参考包括PMOS和NMOS晶体管,其公共浮栅连接到它们的漏极。 弱电流源将电流提供给参考的PMOS晶体管的源极,使得基准PMOS晶体管的源极处的电压等于NMOS和PMOS晶体管的阈值电压(Vtn + Vtp)之和的大小, 参考。 提供了参考的PMOS晶体管的源极处的电压作为对CMOS存储器单元的PMOS晶体管的源极的参考。 为了保证在使用这种参考的CMOS存储器单元之后的后续单元中的零功率操作,在CMOS存储器单元中使用单元注入,并且参考以确保Vtn + Vtp大于或等于Vcc,并且参考电压升高到高于Vcc 。
    • 2. 发明申请
    • A VOLTAGE PROTECTION CIRCUIT
    • 电压保护电路
    • WO1996003750A1
    • 1996-02-08
    • PCT/US1995009366
    • 1995-07-25
    • MICROUNITY SYSTEMS ENGINEERING, INC.BATEMAN, Bruce, L.
    • MICROUNITY SYSTEMS ENGINEERING, INC.
    • G11C05/14
    • G11C5/143G11C7/062
    • A circuit for protecting an interconnect line from certain undesirable voltage swings for a given input signal. A transmission gate is coupled in series between the input signal and the interconnect line. The transmission gate's input terminal is coupled to the input signal, its output terminal is coupled to the interconnect line, and its control terminal is coupled to the output of an inverter. The input of the inverter is coupled to the input signal. When the input signal transitions to a voltage that exceeds the trip point of the inverter, the inverter outputs a signal that disables the transmission gate such that the node is isolated from the input signal. A PFET transmission gate is utilized for protection against voltages that are too negative, and an NFET transmission gate is utilized for protection against voltages that are too positive. The inverter may be replaced by a comparator having its positive input coupled to a reference voltage and its negative input coupled to the input signal. The reference voltage determines the trip point of the protection circuit. The protection circuit may also include first and second biased MOS devices (having different channel types) coupled between first and second working potentials. The gate of the first MOS device is coupled to the input signal and the gate of the second MOS device is coupled to the output of the inverter. The MOS devices function as a conductive voltage divider network to establish a voltage on the node when the node is isolated from the input signal.
    • 用于保护互连线免于给定输入信号的某些不期望的电压摆动的电路。 传输门串联在输入信号和互连线之间。 传输门的输入端耦合到输入信号,其输出端耦合到互连线,其控制端耦合到逆变器的输出。 反相器的输入耦合到输入信号。 当输入信号转换到超过变频器跳闸点的电压时,变频器输出禁止传输门的信号,使得节点与输入信号隔离。 PFET传输门用于防止太负电压的保护,并且NFET传输门被用于防止过大的电压。 反相器可以由比较器代替,其比较器的正输入耦合到参考电压,其负输入耦合到输入信号。 参考电压确定保护电路的跳变点。 保护电路还可以包括耦合在第一和第二工作电位之间的第一和第二偏置MOS器件(具有不同的沟道类型)。 第一MOS器件的栅极耦合到输入信号,第二MOS器件的栅极耦合到反相器的输出端。 MOS器件用作导电分压器网络,以在节点与输入信号隔离时在节点上建立电压。
    • 3. 发明申请
    • DATA STORAGE AND ACCESS SYSTEM
    • 数据存储和访问系统
    • WO1991001556A1
    • 1991-02-07
    • PCT/AU1990000299
    • 1990-07-13
    • TLS TECHNOLOGIES PTY LTDHARRIS, Robert, Jackson
    • TLS TECHNOLOGIES PTY LTD
    • G11C05/14
    • G11C5/142G11C7/00
    • A data storage and access system is described. The system includes a memory unit (5) to which information can be written or from which information can be read. The information is stored in a data store (16). Communication with the memory unit (5) is contactless, and the memory unit (5) requires no fixed internal or connected power supply. Information interaction with the memory unit (5) is by an interrogation unit (34), which provides the power supply required by the memory unit (5) by an electromagnetic induction mechanism. The interrogation unit (34) can provide a user interaction by a user interface unit (36) to read or write information from or to the memory unit (5). Alternatively, information could simply be read or written by an update memory (54) which is later interpreted by conventional means. The exchange of information can be secured by use of security codes and encryption/decryption techniques.
    • 描述了数据存储和访问系统。 该系统包括可以写入信息或从哪个信息被读取的存储器单元(5)。 该信息存储在数据存储器(16)中。 与存储器单元(5)的通信是非接触式的,并且存储器单元(5)不需要固定的内部或连接的电源。 与存储器单元(5)的信息交互是通过询问单元(34),其通过电磁感应机构提供存储器单元(5)所需的电源。 询问单元(34)可以通过用户接口单元(36)提供用户交互以从存储器单元(5)读取或写入信息。 或者,信息可以由更新存储器(54)简单地读取或写入,更新存储器(54)将被传统手段解释。 可以通过使用安全代码和加密/解密技术来保护信息交换。