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1. 发明申请

WO1996042141A1 FIELD PROGRAMMABLE GATE ARRAY (FPGA) HAVING AN IMPROVED CONFIGURATION MEMORY AND LOOK UP TABLE 审中-公开
标题翻译：现场可编程门阵列（FPGA）具有改进的配置存储器和查找表
公开(公告)号：WO1996042141A1
公开(公告)日：1996-12-27
申请号：PCT/US1996009994
申请日：1996-06-07
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , SHARPE-GEISLER, Bradley, A.
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17704
摘要： An FPGA including SRAM memory cells (400), each having a latch configured so that both read and write signals are provided through the data path connection. By providing both read and write through the data path, the FPGA further includes only a single decoder to control pass gates connected to the memory cells (400) during read and write. To prevent voltages during write from damaging pass gates in the data path, the FPGA further includes a modified power supply to provide voltages ranging from VDD to VSS to the memory cell transistors (414, 416, 418, 420) during read, while providing a reduced voltage range during write to enable memory cell states to more easily be altered.
摘要翻译：一种包括SRAM存储单元（400）的FPGA，每个存储单元具有被配置为使得通过数据路径连接提供读取和写入信号的锁存器。通过提供通过数据路径的读取和写入，FPGA进一步仅包括单个解码器，以在读取和写入期间控制连接到存储器单元（400）的通过门。为了防止写入期间的电压在数据路径中的损坏的通过栅极，FPGA还包括修改的电源，以在读取期间向VDD到VSS提供电压到存储单元晶体管（414,416,418,420），同时提供一个在写入期间降低电压范围以使存储单元状态更容易被改变。

2. 发明申请

WO1996038915A1 MACROCELL AND CLOCK SIGNAL ALLOCATION CIRCUIT FOR A PROGRAMMABLE LOGIC DEVICE (PLD) ENABLING PLD RESOURCES TO PROVIDE MULTIPLE FUNCTIONS 审中-公开
标题翻译：用于可编程逻辑器件（PLD）的MACROCELL和时钟信号分配电路启用PLD资源以提供多个功能
公开(公告)号：WO1996038915A1
公开(公告)日：1996-12-05
申请号：PCT/US1996004123
申请日：1996-03-26
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , SHARPE-GEISLER, Bradley, A.
IPC分类号： H03K19/177
CPC分类号： H03K19/1774 , H03K3/037 , H03K3/0375 , H03K3/356156 , H03K19/17704 , H03K19/1778 , H03K19/215
摘要： Output logic macrocells (504) for a programmable logic device as well as a block clock/control circuit (502) which allocates multiple clock signals (CK1-CKN) to each macrocell. Each macrocell includes a multiplexer (506) selectively providing one of the multiple clock signals to a clock input of a storage element (508), which operates similar to a latch. The storage element further receives a sum of product terms output from an OR gate at its data input. Vcc may be provided through the multiplexer to enable the storage element to function in a combinatorial mode. The multiple clock signals may include a clock signal provided to the multiplexer to enable the storage element to function in a latch mode. The clock signal may also be provided through a pulse generator in the block clock/control circuit to provide pulses having a pulse width delta to enable the storage element to function in a D-type flip-flop mode. For the D flip-flop mode, the storage element may be configured to operate as a P-type flip-flop so that its output will change states to follow its data input at a leading edge of its clock input, then does not change states for a period epsilon , wherein epsilon > delta , and then its output will change states to match its data input after the period epsilon if a signal received at the clock input has a period greater than epsilon . To provide reset or preset, a reset or preset signal may be provided at the data input of the storage element, as well as through a second pulse generator in the block clock/control circuit to the clock input of the storage element. The block clock/control circuit may be further configured to provide a dual edge clock mode, a mixed clock mode wherein two signals are provived on a single clock line, or other clocking modes.
摘要翻译：用于可编程逻辑器件的输出逻辑宏单元（504）以及向每个宏单元分配多个时钟信号（CK1-CKN）的块时钟/控制电路（502）。每个宏单元包括多路复用器（506），其选择性地将多个时钟信号中的一个提供给与锁存器相似的存储元件（508）的时钟输入。存储元件还在其数据输入端接收从或门输出的乘积项的和。可以通过多路复用器提供Vcc以使得存储元件能够以组合模式工作。多个时钟信号可以包括提供给多路复用器的时钟信号，以使得存储元件能够以锁存模式工作。时钟信号也可以通过块时钟/控制电路中的脉冲发生器来提供，以提供具有脉冲宽度增量的脉冲，以使得存储元件能够以D型触发器模式工作。对于D触发器模式，存储元件可以被配置为作为P型触发器操作，使得其输出将改变状态以在其时钟输入的前沿跟随其数据输入，然后不改变状态如果在时钟输入处接收到的信号具有大于ε的周期，那么其中ε> delta，然后其输出将改变状态以匹配其周期ε之后的数据输入。为了提供复位或预置，可以在存储元件的数据输入端以及通过块时钟/控制电路中的第二脉冲发生器提供复位或预设信号到存储元件的时钟输入。块时钟/控制电路还可以被配置为提供双边沿时钟模式，其中在单个时钟线上提供两个信号或其它时钟模式的混合时钟模式。

3. 发明申请

WO1996016477A1 INPUT BUFFER FOR A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE 审中-公开
标题翻译：用于高密度可编程逻辑器件的输入缓冲器
公开(公告)号：WO1996016477A1
公开(公告)日：1996-05-30
申请号：PCT/US1995013399
申请日：1995-10-23
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , SHARPE-GEISLER, Bradley, A. , FONTANA, Fabiano
IPC分类号： H03K19/003
CPC分类号： H03K19/00323 , H03K19/0027
摘要： An input buffer which provides compensation for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD). The input buffer includes circuitry to provide an input threshold which varies to compensate for the RC delay of the switch matrix to produce an output which transitions when a signal input to the switch matrix transitions through a predetermined value.
摘要翻译：输入缓冲器，用于对由高密度可编程逻辑器件（PLD）的开关矩阵引入的RC时间延迟进行补偿。输入缓冲器包括提供输入阈值的电路，其变化以补偿开关矩阵的RC延迟，以产生当输入到开关矩阵的信号转变为预定值时转变的输出。

4. 发明申请

WO1996038917A1 VERY HIGH-DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES WITH A MULTI-TIERED HIERARCHICAL SWITCH MATRIX AND OPTIMIZED FLEXIBLE LOGIC ALLOCATION 审中-公开
标题翻译：非常高密度的可编程逻辑器件具有多层次分层开关矩阵和优化的灵活逻辑分配
公开(公告)号：WO1996038917A1
公开(公告)日：1996-12-05
申请号：PCT/US1996004612
申请日：1996-04-03
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , AGRAWAL, Om, P. , SHARPE-GEISLER, Bradley, A. , SCHMITZ, Nicholas, A. , MOYER, Bryon, I.
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704
摘要： A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchical level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.
摘要翻译：一种非常高密度的复杂可编程逻辑器件（CPLD）具有多个层级信号路径。层次结构的最低层次与所有更高层次是独立的。类似地，中间级别与所有较高级别无关，并且仅利用与最低和中级层级相关联的CPLD的资源。第一层级资源包括具有多个输入线和多条输出线的可编程逻辑块以及连接到可编程逻辑块的多条输入线的可编程块开关矩阵。第二层级资源包括连接到可编程块开关矩阵的多个输入线的可编程段开关矩阵。 CPLD另外包括具有连接到第二层级资源的第三层级资源的第三层级电路，其中第三层级信号路径利用第三级，第二级和第一层次级资源。第三层级资源包括可编程全局开关矩阵，其具有可编程地连接到可编程段开关矩阵的线路并与其断开的全局开关矩阵线。

5. 发明申请

WO1996033496A1 REFERENCE FOR CMOS MEMORY CELL HAVING PMOS AND NMOS TRANSISTORS WITH A COMMON FLOATING GATE 审中-公开
标题翻译：具有通用浮动栅的PMOS和NMOS晶体管的CMOS存储单元的参考
公开(公告)号：WO1996033496A1
公开(公告)日：1996-10-24
申请号：PCT/US1996004124
申请日：1996-03-26
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , SHARPE-GEISLER, Bradley, A.
IPC分类号： G11C05/14
CPC分类号： G11C5/147 , G05F3/247
摘要： A voltage reference for a CMOS memory cell having PMOS and NMOS transistors with a common floating gate. The reference provides a more stable voltage than voltage supplied from the Vcc pin of a chip. In one embodiment, the reference includes PMOS and NMOS transistors with a common floating gate connected to their drains. A weak current source supplies current to the source of the PMOS transistor of the reference so that voltage at the source of the PMOS transistor of the reference equals the magnitude of the sum of threshold voltages (Vtn + Vtp) of the NMOS and PMOS transistors of the reference. The voltage at the source of the PMOS transistor of the reference is provided as a reference to the source of the PMOS transistor of the CMOS memory cell. To assure zero power operation in subsequent cells following CMOS memory cells utilizing such a reference, cell implants are utilized in the CMOS memory cells and the reference to assure Vtn + Vtp is greater than or equal Vcc, and voltage to the reference is boosted above Vcc.
摘要翻译：具有具有公共浮动栅极的PMOS和NMOS晶体管的CMOS存储单元的参考电压。该参考电压提供比由芯片的Vcc引脚提供的电压更稳定的电压。在一个实施例中，该参考包括PMOS和NMOS晶体管，其公共浮栅连接到它们的漏极。弱电流源将电流提供给参考的PMOS晶体管的源极，使得基准PMOS晶体管的源极处的电压等于NMOS和PMOS晶体管的阈值电压（Vtn + Vtp）之和的大小，参考。提供了参考的PMOS晶体管的源极处的电压作为对CMOS存储器单元的PMOS晶体管的源极的参考。为了保证在使用这种参考的CMOS存储器单元之后的后续单元中的零功率操作，在CMOS存储器单元中使用单元注入，并且参考以确保Vtn + Vtp大于或等于Vcc，并且参考电压升高到高于Vcc 。

6. 发明申请

WO1996016479A1 SENSE AMPLIFIER AND OR GATE FOR A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE 审中-公开
标题翻译：高密度可编程逻辑器件的感测放大器或门
公开(公告)号：WO1996016479A1
公开(公告)日：1996-05-30
申请号：PCT/US1995013189
申请日：1995-10-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , SHARPE-GEISLER, Bradley, A. , FONTANA, Fabiano
IPC分类号： H03K19/177
CPC分类号： H03K19/17708 , H03K19/018521
摘要： A high density programmable logic device (PLD) having sense amplifiers and OR gates configured to increase operation speed and reduce transistor count from previous circuits as well as to provide a selectable power down mode on a macrocell-by-macrocell basis. The sense amplifiers include a single cascode in the data path connecting a product term of the OR gates. The OR gates utilize a plurality of source follower transistors followed by pass gates to provide logic allocation enabling the sense amplifier outputs to be reduced from the 0.0 V - 5.0 V CMOS rails to increase switching speed while reducing overall transistor count. Amplifying inverters normally provided in the sense amplifiers to provide the CMOS rail-to-rail switching and which would require complex feedback for providing power down on a macrocell-by-macrocell basis are moved forward into OR output circuits. Power down on a macrocell-by-macrocell basis is provided by selectively sizing the amplifying inverters in the OR output circuits.
摘要翻译：具有读出放大器和OR门的高密度可编程逻辑器件（PLD）被配置为增加操作速度并减少来自先前电路的晶体管数量，以及在逐个宏单元的基础上提供可选择的掉电模式。读出放大器包括连接OR门产品项的数据路径中的单个共源共栅。 OR门使用多个源极跟随器晶体管，随后是通过栅极，以提供逻辑分配，使得读出放大器输出能够从0.0V-5.0V CMOS轨道减小，从而提高开关速度，同时降低总体晶体管数量。通常在读出放大器中提供的放大反相器，以提供CMOS轨到轨开关，并且这将需要复杂的反馈以便在宏单元逐宏基础上提供掉电向前进入OR输出电路。通过在OR输出电路中选择性地调整放大逆变器来提供基于宏小区的宏单元的功率下降。

7. 发明申请

WO1997023043A1 CLOCK GENERATOR CIRCUIT USING A PROGRAMMABLY CLOCKED REGISTER 审中-公开
标题翻译：时钟发生器电路使用可编程时钟寄存器
公开(公告)号：WO1997023043A1
公开(公告)日：1997-06-26
申请号：PCT/US1996012528
申请日：1996-07-31
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , SHARPE-GEISLER, Bradley, A.
IPC分类号： H03K05/135
CPC分类号： H03K5/135
摘要： A clock generator circuit for providing a clock signal to a dual-edged D-type flip-flop, enabling the flip-flop to be dual-edged, single-edged, or to enable a user to provide clock edge selection, asynchronous clocking, clock enabling, or a mixture of different type of clock signals. The clock generator circuit includes inputs receiving first and second enable signals and a clock signal. The clock generator circuit further includes circuitry to provide an output clock signal which transitions when a rising edge of a pulse of the clock signal is received when the first clock signal is enabled, or if a falling edge of a pulse of the clock signal is received when the second clock signal is enabled.
摘要翻译：一种用于向双边D型触发器提供时钟信号的时钟发生器电路，使触发器能够被双边形，单边形化，或使得用户能够提供时钟沿选择，异步时钟，时钟使能或不同类型的时钟信号的混合。时钟发生器电路包括接收第一和第二使能信号和时钟信号的输入。时钟发生器电路还包括提供输出时钟信号的电路，当在第一时钟信号被使能时接收到时钟信号的脉冲的上升沿时，或者如果接收到时钟信号的脉冲的下降沿当第二个时钟信号被使能时。

8. 发明申请

WO1996042140A1 FIELD PROGRAMMABLE GATE ARRAY (FPGA) WITH INTERCONNECT ENCODING 审中-公开
标题翻译：具有互连编码的现场可编程门阵列（FPGA）
公开(公告)号：WO1996042140A1
公开(公告)日：1996-12-27
申请号：PCT/US1996009992
申请日：1996-06-07
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , SHARPE-GEISLER, Bradley, A.
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17704 , H03K19/17736
摘要： A method of programming an FPGA to enable encoding of configuration logic block (CLB) outputs enabling an efficient use of FPGA routing resources. The method of the present invention utilizes the one hot approach, wherein only one CLB output is high at a time, to form a state machine using an FPGA. To provide encoding, programmable interconnect points (PIPs) may be programmed to connect CLB outputs to interconnect lines so that the interconnect lines indicate states of the CLB outputs in an encoded form. To provide such encoding, less interconnect lines than CLB outputs provide the encoded form of the CLB outputs. Thus, PIPs can connect a single interconnect line to more than one CLB output. Further, PIPs can connect a single CLB output to interconnect lines provided in separate parallel routing paths. To prevent erroneous results, CLB outputs which are not hot are tri-stated. Output decoding can be provided by an additional decoder in the FPGA connected to the interconnect lines providing the encoded form of the CLB outputs. Output decoding may alternatively be provided using a CLB.
摘要翻译：一种编程FPGA的方法，可以对配置逻辑块（CLB）输出进行编码，从而有效利用FPGA路由资源。本发明的方法利用一种热法，其中一次只有一个CLB输出为高，以形成使用FPGA的状态机。为了提供编码，可编程可编程互连点（PIP）以将CLB输出连接到互连线，使得互连线以编码形式指示CLB输出的状态。为了提供这样的编码，比CLB输出更少的互连线提供CLB输出的编码形式。因此，PIP可以将单个互连线连接到多个CLB输出。此外，PIP可以将单个CLB输出连接到在单独的并行路由路径中提供的互连线。为了防止错误的结果，不是很热的CLB输出是三态的。输出解码可以通过连接到互连线的FPGA中的附加解码器来提供CLB输出的编码形式。也可以使用CLB提供输出解码。

9. 发明申请

WO1996038916A1 A PROGRAMMABLE UNIFORM SYMMETRICAL DISTRIBUTION LOGIC ALLOCATOR FOR A HIGH-DENSITY COMPLEX PLD 审中-公开
标题翻译：高密度复合PLD的可编程均匀对称分配逻辑分配器
公开(公告)号：WO1996038916A1
公开(公告)日：1996-12-05
申请号：PCT/US1996004610
申请日：1996-04-04
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , AGRAWAL, Om, P. , SHARPE-GEISLER, Bradley, A.
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/1737 , H03K19/17704
摘要： A programmable uniform distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable uniform distribution logic allocator provides a uniform number of product terms to each I/O pin of the CPLDs and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable uniform distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e., a selected number of logic product term-clusters, to a programmably selected logic macrocell. Specifically, the programmable uniform distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected to an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines. Also, each programmable router element is programmably connectable to and disconnectable from each of input lines connected to the plurality of programmable router elements so that each output line has access to all input signals on the plurality of input lines.
摘要翻译：可编程均匀分布逻辑分配器增强了包括逻辑分配器在内的非常高密度CPLD的速度，硅利用率，逻辑效率，逻辑利用率和可扩展性。可编程均匀分布逻辑分配器为CPLD的每个I / O引脚提供统一数量的乘积项，并且与反馈相同的统一数量的乘积项。然而，没有产品术语永久连接到特定的宏单元或特定的I / O引脚。可编程均匀分布逻辑分配器包括多个路由器元件，其中每个路由器元件从PAL结构（即选定数量的逻辑乘积项集群）引导所选数量的乘积和项的总和到可编程选择的逻辑宏单元。具体地，可编程均匀分布逻辑分配器具有多条输入线，多条输出线和多条可编程路由器元件。每个可编程路由器元件具有连接到多条输入线中的输入线的输入端和连接到多条输出行中的输出线的输出端。此外，每个可编程路由器元件可编程地连接到可连接到多个可编程路由器元件的每个输入线并且可断开，使得每条输出线可以访问多条输入线上的所有输入信号。

10. 发明申请

WO1996038909A1 CMOS FLIP-FLOP 审中-公开
公开(公告)号：WO1996038909A1
公开(公告)日：1996-12-05
申请号：PCT/US1996004126
申请日：1996-03-26
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , SHARPE-GEISLER, Bradley, A.
IPC分类号： H03K03/356
CPC分类号： H03K3/35606 , H03K3/356156
摘要： A P-type flip-flop, which selectively functions in a D-type flip-flop mode or latch mode depending on its clock signal input. The P-type flip-flop has an output changing states to follow its data input at a leading edge of its clock input, the output then does not change states for a period epsilon , and then the output changing states to match its data input after the period epsilon if a signal is received at its clock input having a period greater than epsilon . With a pulse applied at the clock input having a width less than epsilon , the P-type flip-flop is edge sensitive functioning similar to a D-type flip-flop. With a pulse with longer than epsilon applied to the clock input, the P-type flip-flop appears transparent similar to a latch.
摘要翻译： P型触发器，其选择性地根据其时钟信号输入在D型触发器模式或锁存模式中起作用。 P型触发器具有在其时钟输入的前沿跟随其数据输入的输出改变状态，然后输出不改变周期ε的状态，然后输出改变状态以匹配其之后的数据输入如果在其时钟输入处接收到具有大于ε的周期的信号的周期ε。通过在时钟输入端施加的脉冲具有小于ε的宽度，P型触发器的边缘敏感功能类似于D型触发器。使用长于ε的脉冲施加到时钟输入，P型触发器似乎与锁存器相似。

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