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    • 7. 发明申请
    • DUAL METAL GATE TRANSISTORS FOR CMOS PROCESS
    • 用于CMOS工艺的双金属栅极晶体管
    • WO01097257A2
    • 2001-12-20
    • PCT/US2001/015041
    • 2001-05-10
    • H01L21/28H01L21/336H01L21/8234H01L21/8238H01L27/088H01L27/092H01L29/423H01L29/49H01L
    • H01L21/823842H01L29/66545Y10S977/707Y10S977/721Y10S977/891
    • A process for forming a first transistor (130) of a first conductivity type and a second transistor (132) of a second conductivity type in a semiconductor substrate (102) is disclosed. The substrate (102) has a first well (106) of the first conductivity type and a second well (104) of the second conductivity type. A gate dielectric (108) is formed over the wells. A first metal layer (110) is then formed over the gate dielectric (108). A portion of the first metal layer (110) located over the second well is then removed. A second metal layer (114) different from said first metal is then formed over the wells and a gate mask is formed over the second metal (114). The metal layers (110, 114) are then patterned to leave a first gate over the first well (106) and a second gate over the second well (104). Source/drains (138, 142) are then formed in the first (106) and second (104) wells to form the first (130) and second (132) transistor.
    • 公开了一种在半导体衬底(102)中形成第一导电类型的第一晶体管(130)和第二导电类型的第二晶体管(132)的工艺。 衬底(102)具有第一导电类型的第一阱(106)和第二导电类型的第二阱(104)。 在阱上方形成栅极电介质(108)。 然后在栅极电介质(108)上形成第一金属层(110)。 然后移除位于第二孔上方的第一金属层(110)的一部分。 然后在阱上形成与所述第一金属不同的第二金属层(114),并且在第二金属(114)上形成栅极掩模。 金属层(110,114)然后被图案化以在第一阱(106)上方留下第一栅极,并在第二阱(104)上方留下第二栅极。 然后在第一(106)和第二(104)阱中形成源极/漏极(138,142)以形成第一晶体管(130)和第二晶体管(132)。