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1. 发明申请

WO2007057885A3 METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION 审中-公开
标题翻译：用于多相位错误校正的方法和装置
公开(公告)号：WO2007057885A3
公开(公告)日：2009-09-03
申请号：PCT/IL2006001305
申请日：2006-11-13
申请人： UNIV RAMOT , LITSYN SIMON , SHARON ERAN , ALROD IDAN , LASSER MENACHEM
发明人： LITSYN SIMON , SHARON ERAN , ALROD IDAN , LASSER MENACHEM
IPC分类号： H03M7/00
CPC分类号： H03M13/2927 , G06F11/1068 , H03M13/1111 , H03M13/152 , H03M13/1545 , H03M13/2903 , H03M13/2906 , H03M13/3715 , H03M13/6362
摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
摘要翻译：要编码的数据位被分割成多个子组。每个子组被分别编码以产生相应的码字。所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。最终码字是缩短的码字和浓缩比特的组合。最终码字的表示被分割成选定的子集和多个剩余子集。每个剩余子集被单独解码。如果解码失败之一，则解码失败的剩余子集至少部分地根据所选子集进行解码。如果编码和解码是系统的，则所选择的子集是奇偶校验位。

2. 发明申请

WO2008106320A1 METHOD AND APPARATUS FOR ENCODING AND DECODING DATA 审中-公开
标题翻译：编码和解码数据的方法和装置
公开(公告)号：WO2008106320A1
公开(公告)日：2008-09-04
申请号：PCT/US2008/053815
申请日：2008-02-13
申请人： MOTOROLA, INC. , NIMBALKER, Ajit , BLANKENSHIP, Yufei, W. , CLASSON, Brian, K.
发明人： NIMBALKER, Ajit , BLANKENSHIP, Yufei, W. , CLASSON, Brian, K.
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/2957 , H03M13/2739 , H03M13/2753 , H03M13/2775 , H03M13/2789 , H03M13/2903 , H03M13/6525
摘要： A method and apparatus for turbo encoding with a contention-free interleaver is provided herein. During operation an input block of size K' is received. The original input block and the interleaved input block are encoded to obtain a codeword block, wherein the original input block is interleaved using an interleaver of size K' and a permutation π(i)= ( ƒ 1 x i + ƒ 2 x i 2 ) mod K', where O ≤ i ≤ K'-1 is the sequential index of the symbol positions after interleaving, π(i) is the symbol index before interleaving corresponding to position i, K' is the interleaver size in symbols, and/i and /2 are the factors defining the interleaver. The values of K', ƒ 1 , ƒ 2 are taken from at least one row of a table. The codeword block is transmitted through the channel.
摘要翻译：本文提供了一种用无竞争交织器进行turbo编码的方法和装置。在操作期间，接收大小为K'的输入块。编码原始输入块和交错输入块以获得码字块，其中原始输入块使用大小为K'的交织器和置换p（i）=（1×1×i + mod K'，其中O = i = K'-1是交织后的符号位置的顺序索引，p（i）是符号索引在对应于位置i的交织之前，K'是符号中的交织器大小，并且/ i和/ 2是定义交织器的因子。 K'，＆lt; 1＆gt;，＆lt; 2＆gt; 2的值取自表的至少一行。码字块通过信道传输。

3. 发明申请

WO2007020677A1 送信装置审中-公开
标题翻译：发射器装置
公开(公告)号：WO2007020677A1
公开(公告)日：2007-02-22
申请号：PCT/JP2005/014823
申请日：2005-08-12
申请人：富士通株式会社 , 宮崎俊治 , 大渕一央
发明人：宮崎俊治 , 大渕一央
IPC分类号： H03M13/29
CPC分类号： H03M13/2957 , H03M13/2903 , H03M13/635 , H03M13/653
摘要：　ダミービットが挿入された情報ビットを組織符号化し、該ダミービットを削除してなる組織符号を送信し、受信側において、送信側で削除したダミービットを受信組織符号に挿入して復号する通信システムにおける送信装置である。この送信装置において、ダミービット挿入部は指定の符号化率に基づいて、あるいは物理チャネルの送信レートに基づいて、情報ビットに挿入するダミービットのサイズを決定し、該サイズのダミービットを情報ビットに一様に挿入し、組織符号生成部はダミービットが挿入された情報ビットを組織符号化すると共に、組織ビットより該ダミービットを削除して組織符号を生成して送信する。
摘要翻译：通信系统中的发送装置，其中已经插入了虚拟比特的信息比特被组织编码，然后发送已经从其中去除了伪比特的组织代码; 并且其中，在接收端，在发送端移除的虚拟位被插入到所接收的组织代码中，然后被解码。在发送装置中，伪比特插入部根据指定的编码率或物理信道的传输速率来决定要插入到信息比特中的伪比特的大小，然后将决定大小进入信息位。然后，组织代码生成部分组织地编码已插入虚拟位的信息位，然后从组织位移除虚拟位以生成用于传输的组织代码。

4. 发明申请

WO2006075218A2 CHANNEL ENCODING 审中-公开
标题翻译：频道编码
公开(公告)号：WO2006075218A2
公开(公告)日：2006-07-20
申请号：PCT/IB2005/054421
申请日：2005-12-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , GANDER, Martial , MASSE, Olivier, A. H.
发明人： GANDER, Martial , MASSE, Olivier, A. H.
IPC分类号： H03M13/23
CPC分类号： H03M13/235 , H03M13/23 , H03M13/2903 , H03M13/2957 , H03M13/6505
摘要： A channel encoding method of calculating, using a programmable processor, a code identical with a code obtained with a hardware channel encoder. The method comprises: - a first step (112, 120; 222) of reading the result of a first sub-system of parallel XOR operations between shifted bits in a first pre-computed lookup table at a memory address determined from the value of the inputted bits, the first pre-computed lookup table storing any possible result of the first sub-system at respective memory addresses, and - at least a step (116, 124; 226) of carrying out an XOR operation between the read result and the result of a second sub-system of parallel XOR operations using an XOR instruction of the programmable processor.
摘要翻译：一种使用可编程处理器计算与由硬件信道编码器获得的代码相同的代码的信道编码方法。该方法包括： - 第一步骤（112,120; 222），在第一预先计算的查找表中的移位比特之间读取第一子系统的结果，所述第一子系统在由所述第一预先计算的查找表将所述第一子系统的任何可能的结果存储在相应的存储器地址处，以及至少步骤（116,124; 226），其在所述读取结果和使用可编程处理器的XOR指令的并行XOR操作的第二子系统的结果。

5. 发明申请

WO2004075557A1 ROBUST SYSTEM FOR TRANSMITTING AND RECEIVING MAP DATA 审中-公开
标题翻译：用于发送和接收地图数据的稳健系统
公开(公告)号：WO2004075557A1
公开(公告)日：2004-09-02
申请号：PCT/US2004/004405
申请日：2004-02-17
申请人： ZENITH ELECTRONICS CORPORATION , BRETL, Wayne, E. , FIMOFF, Mark
发明人： BRETL, Wayne, E. , FIMOFF, Mark
IPC分类号： H04N7/24
CPC分类号： H04L51/28 , G01S1/026 , G01S5/021 , G01S5/06 , G02B13/005 , G03G15/5062 , G03G15/5075 , G03G2215/00063 , G03G2215/00067 , G03G2215/00109 , G03G2215/0164 , G06F1/1626 , G06F1/1639 , G06F3/0481 , G06F9/465 , G06F9/5033 , G06F12/109 , G06F21/305 , G06F21/6209 , G06F21/74 , G06F21/88 , G06F2209/5018 , G06F2221/2105 , G06F2221/2115 , G09G5/363 , G11B20/10009 , G11B20/10425 , G11B20/22 , G11B27/034 , H01L27/14625 , H03L7/091 , H03M7/3082 , H03M7/4006 , H03M13/00 , H03M13/23 , H03M13/2764 , H03M13/2771 , H03M13/2903 , H03M13/2993 , H03M13/6356 , H03M13/6362 , H04B1/707 , H04B7/18582 , H04B7/2628 , H04B7/2687 , H04B10/25754 , H04J3/0655 , H04J3/0658 , H04J13/0077 , H04J13/16 , H04L1/0002 , H04L1/0015 , H04L1/0041 , H04L1/0045 , H04L1/0057 , H04L1/006 , H04L1/0066 , H04L1/0068 , H04L1/0071 , H04L1/0072 , H04L1/0075 , H04L1/1685 , H04L1/1841 , H04L1/187 , H04L5/1438 , H04L9/085 , H04L9/304 , H04L12/12 , H04L12/2898 , H04L12/40117 , H04L12/417 , H04L12/462 , H04L12/4641 , H04L25/03038 , H04L25/03343 , H04L25/03866 , H04L25/4902 , H04L25/4904 , H04L25/497 , H04L27/02 , H04L27/156 , H04L27/3416 , H04L29/06 , H04L29/06027 , H04L29/12339 , H04L29/12471 , H04L41/0206 , H04L41/0213 , H04L41/042 , H04L41/046 , H04L41/06 , H04L41/0604 , H04L41/0806 , H04L41/0843 , H04L41/0856 , H04L41/5009 , H04L41/5022 , H04L41/5035 , H04L41/5087 , H04L43/0829 , H04L43/50 , H04L45/04 , H04L45/22 , H04L45/24 , H04L47/10 , H04L47/11 , H04L47/12 , H04L47/14 , H04L47/15 , H04L47/193 , H04L47/2416 , H04L47/2433 , H04L47/27 , H04L47/283 , H04L47/34 , H04L47/70 , H04L47/72 , H04L47/745 , H04L47/765 , H04L47/822 , H04L47/824 , H04L49/90 , H04L49/9094 , H04L51/04 , H04L51/38 , H04L61/2503 , H04L61/2553 , H04L65/1006 , H04L65/1016 , H04L65/1043 , H04L65/1069 , H04L65/1089 , H04L65/1093 , H04L65/4061 , H04L65/4092 , H04L65/605 , H04L65/607 , H04L65/80 , H04L67/1002 , H04L67/1034 , H04L67/306 , H04L67/32 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/166 , H04L69/18 , H04L69/329 , H04L69/40 , H04L2001/0098 , H04L2012/40215 , H04L2012/40273 , H04M1/723 , H04M1/72519 , H04M1/72533 , H04M3/007 , H04M3/10 , H04M3/16 , H04M3/42221 , H04M3/4283 , H04M3/56 , H04M7/0057 , H04M7/1295 , H04M11/06 , H04M2203/2088 , H04M2203/5054 , H04N1/00344 , H04N1/00957 , H04N1/031 , H04N1/0318 , H04N1/1934 , H04N1/1935 , H04N1/32106 , H04N1/40 , H04N5/04 , H04N5/073 , H04N5/126 , H04N5/2251 , H04N5/2257 , H04N5/23248 , H04N5/23254 , H04N5/23258 , H04N5/23267 , H04N5/2327 , H04N5/23277 , H04N5/272 , H04N5/38 , H04N5/44 , H04N5/4401 , H04N5/4446 , H04N5/4448 , H04N5/445 , H04N5/45 , H04N5/455 , H04N5/46 , H04N5/64 , H04N5/642 , H04N5/66 , H04N5/76 , H04N5/775 , H04N5/85 , H04N5/907 , H04N7/0112 , H04N7/0122 , H04N7/147 , H04N7/148 , H04N7/163 , H04N7/17327 , H04N9/3129 , H04N9/641 , H04N9/642 , H04N9/7925 , H04N9/8042 , H04N19/109 , H04N19/115 , H04N19/139 , H04N19/152 , H04N19/174 , H04N19/19 , H04N19/194 , H04N19/51 , H04N19/517 , H04N19/527 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/91 , H04N21/234318 , H04N21/2368 , H04N21/2383 , H04N21/2543 , H04N21/2547 , H04N21/41415 , H04N21/4143 , H04N21/4181 , H04N21/42607 , H04N21/4263 , H04N21/42653 , H04N21/4307 , H04N21/4312 , H04N21/4314 , H04N21/4318 , H04N21/433 , H04N21/4341 , H04N21/43622 , H04N21/43632 , H04N21/4382 , H04N21/44012 , H04N21/440218 , H04N21/4532 , H04N21/458 , H04N21/4621 , H04N21/4623 , H04N21/47211 , H04N21/6175 , H04N21/6187 , H04N21/6582 , H04N21/812 , H04N21/84 , H04N21/854 , H04N2201/0091 , H04N2201/0094 , H04N2201/02493 , H04N2201/03112 , H04N2201/03133 , H04N2201/03141 , H04N2201/03145 , H04N2201/03187 , H04N2201/3212 , H04N2201/3222 , H04N2201/3274 , H04Q3/0025 , H04Q3/60 , H04Q2213/1302 , H04Q2213/13039 , H04Q2213/1304 , H04Q2213/13076 , H04Q2213/13095 , H04Q2213/13109 , H04Q2213/13298 , H04Q2213/13349 , H04R1/028 , H04S7/301 , H04W4/06 , H04W4/10 , H04W4/12 , H04W4/14 , H04W8/245 , H04W8/26 , H04W8/265 , H04W24/00 , H04W28/00 , H04W28/18 , H04W28/24 , H04W28/26 , H04W36/02 , H04W40/00 , H04W40/02 , H04W48/08 , H04W52/0216 , H04W52/0225 , H04W52/0248 , H04W52/0274 , H04W52/30 , H04W56/00 , H04W64/00 , H04W68/00 , H04W72/042 , H04W72/1252 , H04W72/1268 , H04W74/008 , H04W74/0816 , H04W74/0833 , H04W76/10 , H04W76/12 , H04W76/18 , H04W76/20 , H04W76/30 , H04W76/34 , H04W76/45 , H04W80/00 , H04W84/042 , H04W84/08 , H04W84/12 , H04W88/06 , H04W88/08 , H04W88/085 , H04W88/16 , H04W92/02 , H04W92/12 , Y02D70/168 , Y02D70/30 , Y02D70/40 , Y02D70/446 , Y02D70/449 , Y02D70/46 , Y10S370/906 , Y10S370/907 , Y10S707/99943
摘要： Frames comprise odd fields and even fields. The frame sync segments of the odd fields contains a current map specifying the location of data in frames, a next map specifying the location of data in a future frame, and a frame count designating the future frame. The frame sync segments of the even field may contain the same information. Alternatively, the frame sync segments of the odd fields contain the current map and part of the frame count, and the frame sync segments of the corresponding even fields contain the next map and the rest of the frame count. A receiver uses the map and frame count information to find data in the fields of received frames.
摘要翻译：帧包括奇数场和偶数场。奇数场的帧同步段包含指定数据在帧中的位置的当前映射，指定未来帧中的数据的位置的下一个映射以及指定未来帧的帧计数。偶数场的帧同步段可以包含相同的信息。或者，奇数场的帧同步段包含当前映射和帧计数的一部分，并且相应偶数场的帧同步段包含下一个映射，并且剩余的帧计数。接收机使用地图和帧计数信息来查找接收帧的字段中的数据。

6. 发明申请

WO2004038931A3 METHOD AND SYSTEM FOR CODE COMBINING AT AN OUTER DECODER ON A COMMUNICATION SYSTEM 审中-公开
标题翻译：在通信系统中的外部解码器上组合代码的方法和系统
公开(公告)号：WO2004038931A3
公开(公告)日：2004-06-03
申请号：PCT/US0334569
申请日：2003-10-24
申请人： QUALCOMM INC
发明人： WEI YONGBIN , CHEN TAO , TIEDEMANN EDWARD G JR
IPC分类号： H03M13/29 , H04H20/00 , H04L1/00
CPC分类号： H04L1/0045 , H03M13/1515 , H03M13/29 , H03M13/2903 , H03M13/2906 , H04L1/0065
摘要： An outer encoder (612) and an inner encoder (622, 632) encode subsets of information to be transmitted, to improve protection by adding redundancy. The redundancy permits decoding of the information from less than a complete encoded block of information. The use of a combiner 644 at an outer decoder (648) enables better outer decoding of symbols.
摘要翻译：外部编码器（612）和内部编码器（622,632）对要传输的信息的子集进行编码，以通过增加冗余来改进保护。冗余允许从少于完整的编码信息块中解码信息。在外部解码器（648）处使用组合器644使得能够更好地对符号进行外部解码。

7. 发明申请

WO2004038931A2 METHOD AND SYSTEM FOR CODE COMBINING AT AN OUTER DECODER ON A COMMUNICATION SYSTEM 审中-公开
标题翻译：在通信系统上的外部解码器上的代码组合的方法和系统
公开(公告)号：WO2004038931A2
公开(公告)日：2004-05-06
申请号：PCT/US2003/034569
申请日：2003-10-24
申请人： QUALCOMM INCORPORATED
发明人： WEI, Yongbin , CHEN, Tao , TIEDEMANN, Edward, G., Jr.
IPC分类号： H03M13/29
CPC分类号： H04L1/0045 , H03M13/1515 , H03M13/29 , H03M13/2903 , H03M13/2906 , H04L1/0065
摘要： An outer encoder (612) and an inner encoder (622, 632) encode subsets of information to be transmitted, to improve protection by adding redundancy. The redundancy permits decoding of the information from less than a complete encoded block of information. The use of a combiner 644 at an outer decoder (648) enables better outer decoding of symbols.
摘要翻译：外部编码器（612）和内部编码器（622,632）对要发送的信息的子集进行编码，以通过增加冗余来改善保护。冗余允许从小于完整编码的信息块解码信息。在外部解码器（648）处使用组合器644使得能够更好地对符号进行外部解码。

8. 发明申请

WO0186821A3 IMPROVED ERROR FLOOR TURBO CODES 审中-公开
标题翻译：改进的错误地板涡轮编码
公开(公告)号：WO0186821A3
公开(公告)日：2002-04-04
申请号：PCT/US0114405
申请日：2001-05-04
申请人： ICODING TECHNOLOGY INC
发明人： GRAY PAUL K
IPC分类号： H03M13/29 , H04L1/00 , H04L27/20
CPC分类号： H04L1/005 , H03M13/2742 , H03M13/2746 , H03M13/2903 , H03M13/2945 , H03M13/2957 , H03M13/2996 , H03M13/6362 , H04L1/0066 , H04L1/0068 , H04L27/2032
摘要： A turbo code providing very low error rate performance and which can be practically implemented on an integrated circuit is described. In accordance with one embodiment of the invention a turbo code is comprised of three constituent codes and two interleavers placed in parallel concatenated configuration. In a first exemplary embodiment of the invention, the constituent codes are configured with at least one higher rate code and at least one lower rate code. In a second embodiment of the invention, the code is configured with one higher rate code and two lower rate codes. In a third embodiment of the invention, the code is comprised of at least one higher depth constituent code and at least one lower depth constituent code. In a fourth embodiment of the invention, the code is comprised of at least one higher rate and higher depth constituent code.
摘要翻译：描述提供非常低的错误率性能并且可以在集成电路上实际实现的turbo码。根据本发明的一个实施例，turbo码由三个组成码和两个以并行级联配置的交织器组成。在本发明的第一示例性实施例中，构成代码配置有至少一个较高速率代码和至少一个较低速率代码。在本发明的第二实施例中，代码配置有一个较高速率代码和两个较低速率代码。在本发明的第三实施例中，代码包括至少一个较高深度组成码和至少一个较低深度组成码。在本发明的第四实施例中，代码由至少一个较高速率和较高深度的组成码构成。

9. 发明申请

WO02019539A1 SOFT-OUTPUT DECODER 审中-公开
标题翻译：软输出解码器
公开(公告)号：WO02019539A1
公开(公告)日：2002-03-07
申请号：PCT/JP2001/007576
申请日：2001-08-31
IPC分类号： G06F11/10 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/39 , H03M13/45
CPC分类号： H03M13/2957 , H03M13/27 , H03M13/2903 , H03M13/6566
摘要： The position where the code is deleted is appropriately expressed through a simple constitution of a small circuit scale. A soft-output decoding circuit (90) of an element decoder has a reception value and prior probability information selecting circuit (154) for selecting an inputted decoding reception value TSR, extrinsic information, or interleave data TEXT as information necessary for soft-output decoding. The reception value and prior probability information selecting circuit (154) replaces the data at which no code output is present because of, e.g., puncture with a symbol having a likelihood of 0 according to intrinsic erasure position information IERS supplied from an intrinsic erasure information generating circuit (152). Consequently, the reception value and prior probability information selecting circuit (154) outputs information representing that the probability that the bit at the position where no code output is present is 0 or 1 is 1/2 .
摘要翻译：代码被删除的位置通过小电路规模的简单结构适当地表示。元件解码器的软输出解码电路（90）具有接收值和先验概率信息选择电路（154），用于选择输入的解码接收值TSR，外在信息或交织数据TEXT作为软输出解码所需的信息。接收值和先验概率信息选择电路（154）由于根据从内在擦除信息生成提供的固有擦除位置信息IERS，例如用具有0的似然度的符号进行穿孔而替换不存在代码输出的数据电路（152）。因此，接收值和先验概率信息选择电路（154）输出表示在不存在代码输出的位置处的位为0或1的概率为1/2的信息。

10. 发明申请

WO02019537A1 INTERLEAVING APPARATUS 审中-公开
标题翻译：交互式设备
公开(公告)号：WO02019537A1
公开(公告)日：2002-03-07
申请号：PCT/JP2001/007574
申请日：2001-08-31
IPC分类号： G06F11/10 , H03M13/27 , H03M13/29 , H03M13/39 , H03M13/41 , H03M13/45 , H04L1/00
CPC分类号： H03M13/2767 , H03M13/235 , H03M13/2771 , H03M13/2903 , H03M13/2987 , H03M13/3911 , H03M13/3927 , H03M13/3988 , H03M13/41 , H03M13/6516 , H03M13/6566 , H03M13/6572 , H04L1/0043 , H04L1/0052 , H04L1/0055 , H04L1/0059 , H04L1/0066 , H04L1/0071
摘要： Interleave of plural types are realized, and decoding adaptively corresponding to codes of various types is conducted through a simple constitution. An interleaver (100) of an element decoder has a plurality of storage circuits (407) where data is stored, a control circuit (400) for generating address data for writing data in the storage circuits (407) and address data for reading the data from the storage circuits (407), an address selecting circuit (405) for selecting address data to be distributed to the storage circuits (407) in accordance with the mode indicating the structure of codes including the type of interleave to be conducted, an input data selecting circuit (406) for selecting data to be distributed to the storage circuits (407) in accordance with the mode, and an output data selecting circuit (408) for selecting data to be outputted in accordance with the mode. A storage circuit to be used is selected from among the storage circuits (407).
摘要翻译：实现多种类型的交织，通过简单的结构进行与各种代码自适应对应的解码。元件解码器的交织器（100）具有存储数据的多个存储电路（407），用于产生用于在存储电路（407）中写入数据的地址数据的控制电路（400）和用于读取数据的地址数据从存储电路（407），地址选择电路（405），用于根据指示要进行的交织类型的代码的结构的模式，选择要分配给存储电路（407）的地址数据，输入数据选择电路（406），用于根据该模式选择要分配给存储电路（407）的数据;以及输出数据选择电路（408），用于根据该模式选择要输出的数据。从存储电路（407）中选择要使用的存储电路。

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