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1. 发明申请

WO2011010286A3 COMPACT DECODING OF PUNCTURED CODES 审中-公开
标题翻译：伪码的紧凑解码
公开(公告)号：WO2011010286A3
公开(公告)日：2011-11-24
申请号：PCT/IB2010053317
申请日：2010-07-21
申请人： UNIV RAMOT , SHARON ERAN , ALROD IDAN , LITSYN SIMON
发明人： SHARON ERAN , ALROD IDAN , LITSYN SIMON
IPC分类号： H03M13/00 , H03M13/25 , H04L1/00
CPC分类号： H03M13/1185 , H03M13/1111 , H03M13/616 , H03M13/6362 , H03M13/6393 , H04L1/0013 , H04L1/0052 , H04L1/0057 , H04L1/0069
摘要： k input bits are encoded according to a code with which is associated a m x n=m+k parity check matrix H. The resulting codeword is punctured, with n' bits. The punctured codeword is exported to a corrupting medium such as a communication channel or a memory. A representation of the punctured codeword is imported from the corrupting medium and is decoded using a matrix H' that is smaller than H. For example, H' is m'=m~(n-n ') x n' and is derived by merging selected rows of H. Alternatively, H has at most m rows and fewer than n columns but more than n' columns. Alternatively, H has fewer than m'=m-(n-n') rows and fewer than n' columns.
摘要翻译： k个输入比特根据与m×n = m + k个奇偶校验矩阵H相关联的代码进行编码。所产生的码字用n'比特打孔。删截的码字被导出到诸如通信信道或存储器之类的破坏媒体。删截码字的表示从破坏介质导入并使用小于H的矩阵H'解码。例如，H'是m'= m〜（nn'）×n'并且通过合并选择的行的H.或者，H具有至多m行，少于n列但多于n'列。或者，H具有少于m'= m-（n-n'）行且少于n'列。

2. 发明申请

WO2009156935A1 USING DAMPING FACTORS TO OVERCOME LDPC TRAPPING SETS 审中-公开
标题翻译：使用阻尼因子来覆盖LDPC陷波器组
公开(公告)号：WO2009156935A1
公开(公告)日：2009-12-30
申请号：PCT/IB2009052662
申请日：2009-06-22
申请人： UNIV RAMOT , SHARON ERAN , LITSYN SIMON , ALROD IDAN
发明人： SHARON ERAN , LITSYN SIMON , ALROD IDAN
IPC分类号： H03M13/11
CPC分类号： H03M13/1137 , H03M13/1114 , H03M13/114 , H03M13/3753 , H03M13/618 , H03M13/6362 , H03M13/658
摘要： To decode a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between JV bit nodes and N-K check nodes of a graph in a plurality of iterations. In each of one or more of the iterations, some or all values associated with the bit nodes, and/or some or all values associated with check nodes, and/or some or all messages are modified in a manner that depends explicitly on the ordinality of the iteration and is independent of any other iteration. Alternatively, the modifications are according to respective locally heteromorphic rules.
摘要翻译：为了将从信道导入的表示解码为将K个信息比特编码为N> K个码字比特的码字，通过在图中的JV比特节点和NK校验节点之间交换消息来更新码字比特的估计，迭代。在一个或多个迭代中的每一个中，与位节点相关联的一些或所有值，和/或与校验节点相关联的一些或所有值和/或某些或所有消息以明确依赖于序数的方式被修改的迭代，并且独立于任何其他迭代。或者，修改根据各自的本地异形规则。

3. 发明申请

WO2008142683A3 MEMORY-EFFICIENT LDPC DECODING 审中-公开
标题翻译：存储器高效的LDPC解码
公开(公告)号：WO2008142683A3
公开(公告)日：2009-02-12
申请号：PCT/IL2008000685
申请日：2008-05-20
申请人： UNIV RAMOT , SHARON ERAN , LITSYN SIMON , ALROD IDAN
发明人： SHARON ERAN , LITSYN SIMON , ALROD IDAN
IPC分类号： H03M13/11
CPC分类号： H03M13/114 , H03M13/6505
摘要： To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N-K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.
摘要翻译：为了将编码K个信息比特的码字的表示解码为N个K个码字比特，消息在其中E个边缘连接比特节点和校验节点的图的N个比特节点和N-K个校验节点之间进行交换。当消息被交换时，存储少于E个消息，和/或存储少于N个码字比特的软估计。在一些实施例中，消息仅在子图中以及子图和一个或多个外部校验节点之间交换。当消息被交换时，最大数量的存储消息是具有最多边缘的子图中的边数加上将子图连接到外部校验节点的边数，和/或最大存储的软估计数是具有最多位节点的子图中的比特节点的数量。

4. 发明申请

WO2008081426B1 AVOIDING ERRORS IN A FLASH MEMORY BY USING SUBSTITUTION TRANSFORMATIONS 审中-公开
标题翻译：通过使用替代变换避免闪存中的错误
公开(公告)号：WO2008081426B1
公开(公告)日：2008-08-14
申请号：PCT/IL2007001567
申请日：2007-12-19
申请人： UNIV RAMOT , ALROD IDAN , SHARON ERAN , LITSYN SIMON
发明人： ALROD IDAN , SHARON ERAN , LITSYN SIMON
IPC分类号： G06F11/10 , G11C7/10 , G11C11/56
CPC分类号： G11C11/5628 , G06F11/1072 , G11C7/1006 , G11C29/00
摘要： Memory circuitry, or a memory device controller, or a host of a memory device, store an input string of M N-tuples of bits by selecting a substitution transformation in accordance with the input string and by applying the transformation to the input string to provide a transformed string of M N-tuples of bits. M or more memory cells are programmed to represent the transformed string and preferably also to represent a key of the transformation. Alternatively, the circuitry selectively programs each of M or more cells to a respective one of 2N states. The circuitry or the controller selects a mapping that maps the binary numbers in [0,2N-1] into respective states in accordance with the input string and the circuitry uses the mapping to program M cells to represent the input string. Preferably, a key of the mapping is stored in the memory in association with the M cells.
摘要翻译：存储器电路或存储器件控制器或存储器件的主机通过根据输入字符串选择替换变换并通过将变换应用于输入字符串来存储M个N元组的输入串，以提供一个M位元组的变换字符串。 M个或更多个存储器单元被编程以表示变换的字符串，并且优选地也表示转换的关键字。或者，电路选择性地将M个或更多个单元中的每一个编程为2N个状态中的相应的一个。电路或控制器根据输入字符串选择将[0,2N-1]中的二进制数映射到各自状态的映射，并且电路使用映射来编程M个单元来表示输入字符串。优选地，映射的密钥与M个单元相关联地存储在存储器中。

5. 发明申请

WO2004112040A3 METHODS OF INCREASING THE RELIABILITY OF A FLASH MEMORY 审中-公开
公开(公告)号：WO2004112040A3
公开(公告)日：2004-12-23
申请号：PCT/IL2004/000530
申请日：2004-06-17
申请人： M-SYSTEMS FLASH DISK PIONEERS LTD. , BAN, Amir , LITSYN, Simon , ALROD, Idan
发明人： BAN, Amir , LITSYN, Simon , ALROD, Idan
IPC分类号： G11C16/04
摘要： A multi-level flash memory cell is read by comparing the cell's threshold voltage (111, 110, 101, 100, 011, 010, 001, 000) to a plurality of integral reference voltages (Vmin, V1, V2, V3, V4, V5, V6, V7, and Vmax) and to a fractional reference voltage (V0.5, V1.5, V2.5, V3.5, V4.5, V5.5, V6.5, and V7.5). Multi-level cells of a flash memory are programmed collectively with data and redundancy bits at each significance level, preferably with different numbers of data and redundancy bits at each significance level. The cells are read collectively, from lowest to highest significance level, by correcting the bits at each significance level according to the redundancy bits and adjusting the bits of the higher significance levels accordingly. The adjustment following the correction of the least significant bits is in accordance with comparisons of a cell's threshold voltages to fractional reference voltages.

6. 发明申请

WO2013018080A1 ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS 审中-公开
标题翻译：具有减少内存和电源要求的错误修正解码
公开(公告)号：WO2013018080A1
公开(公告)日：2013-02-07
申请号：PCT/IL2011/000617
申请日：2011-07-31
申请人： SANDISK TECHNOLOGIES, INC., A TEXAS CORPORATION , SHARON, Eran , ALROD, Idan , FAINZILBER, Omer , LITSYN, Simon
发明人： SHARON, Eran , ALROD, Idan , FAINZILBER, Omer , LITSYN, Simon
IPC分类号： H03M13/00
CPC分类号： H03M13/1105 , H03M13/1117 , H03M13/3715 , H03M13/6502
摘要： An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations.
摘要翻译：提供了一种示例性方法，其包括接收包括多个比特的码字的表示，并且将比特与表示比特的相应多个一比特硬比特值和表示多个比特的度量的多比特软比特值相关联各个硬比特值的可靠性。该方法包括用于多个迭代中的每一个，作为该子集的比特的当前硬比特值的函数来更新比特的相应子集的一个或多个比特的硬比特/软比特值，以及当前相应位的硬比特和软比特值。对于两次迭代，其中对于两次迭代的子集的每个位的当前硬比特和软比特值是相同的，则在两次迭代之一期间为子集的任何比特更新的硬比特/软比特值与在两次迭代中的另一个中相应位计算的相同。

7. 发明申请

WO2011128867A1 MULTIPLE PROGRAMMING OF FLASH MEMORY WITHOUT ERASE 审中-公开
标题翻译：无擦除的闪存存储器的多个编程
公开(公告)号：WO2011128867A1
公开(公告)日：2011-10-20
申请号：PCT/IB2011/051613
申请日：2011-04-14
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , ALROD, Idan , LITSYN, Simon , ILANI, Ishai
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon , ILANI, Ishai
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/102 , G06F12/02 , G11C11/5628 , G11C16/349
摘要： To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.
摘要翻译：为了顺次地在多个存储单元中存储数量相等的第一和第二多个输入位，第一变换将第一输入位变换为第一多个变换位。单元的第一部分被编程为根据位序列到单元级别的映射来存储第一变换的位，但是如果第一变换具有可变的输出长度，则只有当足够少的第一变换位适合于第一细胞部分。然后，在不擦除包括第一部分的第二单元部分的情况下，如果根据映射通过第二输入位的第二变换获得的表示第二多个变换位的第二部分的单元的各个级别是从当前单元级可访问，第二部分被编程为存储第二转换位。

8. 发明申请

WO2010092536A1 APPARATUS AND METHOD FOR ENHANCING FLASH ENDURANCE BY ENCODING DATA 审中-公开
标题翻译：通过编码数据提高闪存耐久性的装置和方法
公开(公告)号：WO2010092536A1
公开(公告)日：2010-08-19
申请号：PCT/IB2010/050621
申请日：2010-02-11
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , LITSYN, Simon , ALROD, Idan
发明人： SHARON, Eran , LITSYN, Simon , ALROD, Idan
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G06F12/0246 , G11C7/1006 , G11C11/5628 , G11C16/349 , G11C16/3495 , G11C2211/5647
摘要： Input bits are stored in memory cells by mapping the input bits into a larger number of transformed bits using a shaping encoding that has a downward asymptotic bias with respect to a mapping of bit patterns to cell states and programming some of the cells according to that mapping of bit patterns to cell states. The programmed cells are erased before being programmed to store any other bits. The invention sacrifices memory capacity to increase endurance.
摘要翻译：通过使用相对于位模式对单元状态的映射具有向下渐近偏移的整形编码并根据该映射来编程一些单元，将输入位存储在存储器单元中，将输入位映射到更大数目的变换位中的位模式到单元状态。在被编程为存储任何其他位之前，编程的单元被擦除。本发明牺牲记忆能力以增加耐力。

9. 发明申请

WO2010035241A1 METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES 审中-公开
标题翻译：闪存中自适应编码的方法和系统
公开(公告)号：WO2010035241A1
公开(公告)日：2010-04-01
申请号：PCT/IB2009/054222
申请日：2009-09-27
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, menahem
发明人： LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, menahem
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3404 , G06F11/1072 , G11C7/1006 , G11C11/5628 , G11C29/00 , G11C2211/5641
摘要： Bits are stored by attempting to set parameter value(s) of (a) cell(s) to represent some of the bits. In accordance with the attempt, an adaptive mapping of the bits to value ranges is provided and the value(s) is/are adjusted accordingly as needed. Or, to store (a) bit(s) in (a) cell(s), a default mapping of the bit(s) to a predetermined set of value ranges is provided and an attempt is made to set the cell value(s) accordingly. If, for one of the cells, the attempt sets the value such that the desired range is inaccessible, an adaptive mapping is provided such that the desired range is accessible. Or, to store (a) bit(s) in (a) cell(s), several mappings of the bϊt(s) to a predetermined set of ranges is provided. Responsive to an attempt to set the cell value(s) according to one of the mappings, the mapping to actually use is selected.
摘要翻译：通过尝试设置（a）单元的参数值来表示某些位来存储位。根据该尝试，提供了比特到值范围的自适应映射，并且根据需要相应地调整该值。或者，为了将（a）位（a）存储在（a）单元中，提供了该位的默认映射到预定的一组值范围，并尝试设置单元值（s ）。如果对于其中一个小区，尝试将值设置为使得期望的范围不可访问，则提供自适应映射，使得期望的范围是可访问的。或者，为了将（a）位（a）存储在（a）单元中，提供了b≤t（s）的几个映射到预定的范围集合。响应于根据映射之一设置单元格值，选择实际使用的映射。

10. 发明申请

WO2007102141A3 MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING 审中-公开
标题翻译：具有非定向映射的多位单元闪速存储器件
公开(公告)号：WO2007102141A3
公开(公告)日：2009-04-09
申请号：PCT/IL2006001251
申请日：2006-10-30
申请人： UNIV RAMOT , LITSYN SIMON , SHARON ERAN , ALROD IDAN
发明人： LITSYN SIMON , SHARON ERAN , ALROD IDAN
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G06F11/1072 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C16/0483 , G11C16/34 , G11C29/42 , G11C2211/5641
摘要： To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to one or may be an "into" generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.
摘要翻译：为了存储多个输入位，这些位被映射到一个或多个存储器单元的相应的编程状态，并且单元被编程为相应的编程状态。映射可以是多对一的，或者可以是“到”广义灰色映射。读取单元以提供被转换成多个输出位的读取状态值，例如通过最大似然解码或通过将读取状态值映射到多个软比特中，然后解码软比特。

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