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1. 发明申请

WO2002091592A1 LOW DENSITY PARITY CHECK CODES AND LOW DENSITY TURBO PRODUCT CODES 审中-公开
标题翻译：低密度奇偶校验码和低密度涡轮产品编码
公开(公告)号：WO2002091592A1
公开(公告)日：2002-11-14
申请号：PCT/US2002/014614
申请日：2002-05-09
申请人： ADVANCED HARDWARE ARCHITECTURES, INC.
发明人： KHANNANOV, Roman R. , MARKARIAN, Garik , ORTYUKOV, Sergey I. , PICKAVANCE, Keith , PORTNEY, Sergey L.
IPC分类号： H03M13/00
CPC分类号： H03M13/2963 , H03M13/1102 , H03M13/1105 , H03M13/2987 , H03M13/6561
摘要： A method of and apparatus for encoding a one dimensional input codeword into an output codeword, wherein the output codeword includes an output codeword bit comprising the steps of receiving the input codeword, wherein the input codeword includes an input codeword bit; creating a generator matrix (200), wherein the generator matrix includes a parity matrix (204) having a plurality of parity bits; combining the input codeword bit and a corresponding parity bit from the plurality of parity bits, thereby generating an output redundant bit associated with the output codeword bit; transmitting the input codeword bit; and transmitting the output redundant bit.
摘要翻译：一种用于将一维输入码字编码为输出码字的方法和装置，其中所述输出码字包括输出码字比特，包括接收所述输入码字的步骤，其中所述输入码字包括输入码字比特; 创建生成矩阵（200），其中生成矩阵包括具有多个奇偶校验位的奇偶校验矩阵（204）; 从所述多个奇偶校验位组合所述输入码字比特和对应的奇偶校验位，从而生成与所述输出码字比特相关联的输出冗余比特; 发送所述输入码字比特; 并发送输出冗余位。

2. 发明申请

WO01059935A2 A SYSTEM AND METHOD EMPLOYING A MODULAR DECODER FOR DECODING TURBO AND TURBO-LIKE CODES IN A COMMUNICATIONS NETWORK 审中-公开
标题翻译：采用模块化解码器的系统和方法，用于解码通信网络中的涡轮和涡轮代码
公开(公告)号：WO01059935A2
公开(公告)日：2001-08-16
申请号：PCT/US2001/004381
申请日：2001-02-12
IPC分类号： H03M13/00 , H03M13/29 , H03M13/45
CPC分类号： H03M13/2987 , H03M13/296 , H03M13/2966 , H03M13/2981 , H03M13/6362
摘要： A system and method for decoding encoded data, employing a parser and at least one decoder. The parser receives and parses the encoded data into a plurality of parsed data streams, with each of the parsed data streams including a portion of said encoded data. The decoder decodes the parsed data streams based on at least information included in the parsed data streams to provide decoded data which includes soft decision data. The decoder can perform a respective decoding iteration on each respective one of the parsed data streams to provide the decoded data, and can perform such decoding iterations based on additional information, such as parity information, pertaining to the data in the parsed data streams. Alternatively, the decoder can include a plurality of decoders, each adapted to decode a respective one of the parsed data streams to output a respective decoded data stream as a portion of the decoded data. The system and method alternatively can be configured without a parser, and can employ at least one soft decoder module and another decoder module. The soft decoder module can perform multiple decoding iterations on the encoded data to provide soft decision data relating to the encoded data, without providing any hard decision data, and the other decoder module decodes the encoded data based on the soft decision data to provide hard decoded data representative of a decoded condition of said encoded data and/or soft decision data relating to said encoded data.
摘要翻译：一种用于解码编码数据的系统和方法，使用解析器和至少一个解码器。解析器接收并将编码数据解析为多个解析数据流，每个解析数据流包括所述编码数据的一部分。解码器至少基于解析的数据流中包含的信息解码解析的数据流，以提供包括软判决数据的解码数据。解码器可以对每个解析的数据流执行相应的解码迭代以提供解码的数据，并且可以基于与解析的数据流中的数据有关的附加信息（诸如奇偶校验信息）来执行这样的解码迭代。或者，解码器可以包括多个解码器，每个解码器适于对解析的数据流中的相应数据流进行解码，以将相应的解码数据流作为解码数据的一部分输出。可以配置系统和方法而不需要解析器，并且可以使用至少一个软解码器模块和另一个解码器模块。软解码器模块可以对编码数据执行多个解码迭代，以提供与编码数据相关的软判决数据，而不提供任何硬判决数据，而另一解码器模块基于软判决数据解码编码数据，以提供硬解码代表所述编码数据的解码条件的数据和/或与所述编码数据有关的软判决数据。

3. 发明申请

WO2009124376A1 SOFT THERMAL FAILURE IN A HIGH CAPACITY TRANSMISSION SYSTEM 审中-公开
标题翻译：高容量传输系统中的软热故障
公开(公告)号：WO2009124376A1
公开(公告)日：2009-10-15
申请号：PCT/CA2009/000347
申请日：2009-03-20
申请人： NORTEL NETWOKS LIMITED , ROBERTS, Kim, B.
发明人： ROBERTS, Kim, B.
IPC分类号： H03K17/14 , H04B10/02
CPC分类号： H03K19/00369 , H03K2017/0806 , H03M13/29 , H03M13/2951 , H03M13/2975 , H03M13/2987 , H03M13/3707
摘要： A method of managing operation of an Integrated Circuit (IC) designed to process a signal. A temperature of the IC is detected, and signal processing performed by the IC adjusted based on the detected temperature.
摘要翻译：管理设计用于处理信号的集成电路（IC）的操作的方法。检测IC的温度，并根据检测到的温度调整由IC进行的信号处理。

4. 发明申请

WO2004062111A1 HIGH SPEED TURBO CODES DECODER FOR 3G USING PIPELINED SISO LOG-MAP DECODERS ARCHITECTURE 审中-公开
标题翻译：使用流水线SISO LOG-MAP解码器架构的3G高速Turbo码解码器
公开(公告)号：WO2004062111A1
公开(公告)日：2004-07-22
申请号：PCT/US2003/035865
申请日：2003-11-07
申请人： ICOMM TECHNOLOGIES, INC.
发明人： NGUYEN, Quang
IPC分类号： H03M13/00
CPC分类号： H03M13/3927 , H03M13/2771 , H03M13/2987 , H03M13/3905 , H03M13/3922 , H03M13/3961 , H03M13/6306 , H03M13/6563 , H04L1/005 , H04L1/0052 , H04L1/0054 , H04L1/0055 , H04L1/0066 , H04L1/0071
摘要： The invention encompasses several improved Turbo Codes Decoder method and apparatus to provide a more suitable, practical and simpler method for implementing a Turbo Codes Decoder in ASIC or DSP codes. (1) Two Parallel Turbo Codes Decoder blocks (40A & 40B) to compute soft-decoded data RXDa, RXDb from two different received path. (2) Two pipelined Log-MAP decoders (A42 & B44) are used for iterative decoding received data. (3) A Sliding Window of block N data are used on the input memory for pipeline operations. (4) The output Block N Data from the first decoder A are stored in the RAM memory A, and the second decoder B stores output data in the RAM memory B while the decoder B decodes block N data from RAM memory A at the same clock cycle. (5) Log-Map decoders are simpler to implement and are low-power consumption. (6) Pipelined log-Map decoder’s architecture provides high-speed data throughout, one output per clock cycle.
摘要翻译：本发明包括若干改进的Turbo码解码器方法和装置，以提供用于在ASIC或DSP码中实现Turbo码解码器的更合适，实用和更简单的方法。（1）两个并行Turbo码解码器块（40A和40B），以从两个不同的接收路径计算软解码数据RXDa，RXDb。（2）使用两个流水线Log-MAP解码器（A42和B44）迭代解码接收到的数据。（3）在输入存储器上使用块N数据的滑动窗口进行流水线操作。（4）来自第一解码器A的输出块N数据存储在RAM存储器A中，第二解码器B将输出数据存储在RAM存储器B中，而解码器B在同一时钟解码来自RAM存储器A的块N数据周期。（5）Log-Map解码器更易于实现并且功耗低。（6）流水线日志 - 地图解码器的架构提供了高速数据，每个时钟周期一个输出。

5. 发明申请

WO00064058A1 ENCODER AND DECODER 审中-公开
标题翻译：编码器和解码器
公开(公告)号：WO00064058A1
公开(公告)日：2000-10-26
申请号：PCT/JP1999/002034
申请日：1999-04-16
IPC分类号： H03M13/29 , H04L1/00 , H03M13/22 , H03M13/12
CPC分类号： H04L1/005 , H03M13/27 , H03M13/2903 , H03M13/2957 , H03M13/2987 , H03M13/353 , H03M13/6362 , H04L1/0009 , H04L1/0041 , H04L1/0065 , H04L1/0066 , H04L1/0069
摘要： An encoder (100) outputs source data (u) with appended parity data. The parity data is generated according to the outputs from a first encoder section (101) and a second encoder section (102). The first encoder section (101) encodes source data (u). The second encoder section (102) encodes source data (u) randomized by a plurality of interleavers (103-1)-(103-m) connected in parallel. The interleavers (103-1)-(103-m) randomize the data in mutually different manners.
摘要翻译：编码器（100）输出具有附加奇偶校验数据的源数据（u）。根据来自第一编码器部分（101）和第二编码器部分（102）的输出产生奇偶校验数据。第一编码器部分（101）对源数据（u）进行编码。第二编码器部分（102）编码由并行连接的多个交织器（103-1） - （103-m）随机化的源数据（u）。交织器（103-1） - （103-m）以相互不同的方式随机化数据。

6. 发明申请

WO2014002043A1 DETERMINING CONTROL BITS OF BUTTERFLY NETWORKS FOR PARALLEL TURBO DECODING 审中-公开
标题翻译：确定平行涡轮解码的黑客网络的控制位
公开(公告)号：WO2014002043A1
公开(公告)日：2014-01-03
申请号：PCT/IB2013/055279
申请日：2013-06-27
申请人： RENESAS MOBILE CORPORATION , NIEMINEN, Esko Juhani
发明人： NIEMINEN, Esko Juhani
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/2775 , H03M13/276 , H03M13/2764 , H03M13/2789 , H03M13/2957 , H03M13/2987 , H03M13/6561
摘要： Control bits for switches of a butterfly network are directly solved (314) iteratively for each successive functional column of switches to route data values in parallel according to a multiple access scheme through the butterfly network to memory spaces. A memory space address and appended bus index leading into the butterfly network are generated. A linear order bus index and a physical address are determined for a switch having an unsolved control bit. The solved control bits are applied to solve control bits to a next functional column in a linear order and an interleaved order by starting from the bus index and physical address. The linear order is moved to the interleaved order by a reduced turbo de-interleaver and the interleaved order is moved to the linear order by a reduced turbo interleaver until solving a sequence of control bits related to the start bus index and the start physical address.
摘要翻译：蝶形网络的交换机的控制位直接针对每个连续的交换机功能列进行迭代，以根据多址方案通过蝶形网络将数据值并行布置到存储器空间。生成通向蝶形网络的存储空间地址和附加总线索引。为具有未解决的控制位的开关确定线性次序总线索引和物理地址。通过从总线索引和物理地址开始，将解决的控制位应用于以线性顺序和交错顺序将控制位解析为下一个功能列。通过减少的turbo解交织器将线性顺序移动到交织顺序，并且通过减少的turbo交织器将交错顺序移动到线性顺序，直到求解与起始总线索引和起始物理地址相关的控制位序列。

7. 发明申请

WO2007117965A1 SCHEDULING PIPELINED STATE UPDATE FOR HIGH-SPEED TRELLIS PROCESSING 审中-公开
标题翻译：调度管道状态更新用于高速TRELLIS加工
公开(公告)号：WO2007117965A1
公开(公告)日：2007-10-18
申请号：PCT/US2007/064843
申请日：2007-03-23
申请人： TRELLISWARE TECHNOLOGIES, INC. , DIMOU, Georgios, D.
发明人： DIMOU, Georgios, D.
IPC分类号： H03M13/41 , H03M13/39 , H04L1/00
CPC分类号： H03M13/4107 , H03M13/03 , H03M13/2987 , H03M13/3905 , H03M13/3922 , H03M13/41 , H03M13/6502
摘要： Methods, apparatuses, and systems are presented for extracting information from a received signal resulting from a process capable of being represented as a finite state machine having a plurality of states, wherein transitions between the states can be represented by a trellis spanning a plurality of time indices, involving calculating branch metrics taking into account the received signal, calculating state metrics at each time index by taking into account the branch metrics and using a pipelined process, wherein the pipelined process is used to calculate state metrics at a first time index, wherein the pipelined process is then used to calculate state metrics at one or more non-adjacent time indices, and wherein the pipelined process is then used to calculate state metrics at an adjacent time index, and generating at least one output taking into account state metrics for states associated with at least one selected path through the trellis.
摘要翻译：呈现方法，装置和系统，用于从由能够被表示为具有多个状态的有限状态机的处理得到的接收信号中提取信息，其中状态之间的转换可以由跨越多个时间的网格来表示索引，涉及考虑所接收到的信号来计算分支度量，通过考虑分支度量并使用流水线过程来计算每个时间索引处的状态度量，其中流水线过程用于计算第一时间索引处的状态度量，其中流水线过程然后用于计算一个或多个非相邻时间索引处的状态度量，并且其中流水线处理然后用于计算相邻时间索引的状态度量，并且考虑到至少一个输出，考虑到与通过网格的至少一个所选路径相关联的状态。

8. 发明申请

WO01045272A1 INTERLEAVER DESIGN FOR PARSED PARALLEL CONCATENATED CODES 审中-公开
标题翻译：用于并行并行编码的交互设计
公开(公告)号：WO01045272A1
公开(公告)日：2001-06-21
申请号：PCT/US2000/034303
申请日：2000-12-14
IPC分类号： H03M13/27 , H03M13/29 , H04L1/00
CPC分类号： H04L1/0041 , H03M13/2746 , H03M13/2771 , H03M13/296 , H03M13/2987 , H03M13/6362 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： A method and apparatus for interleaving an input data stream for parsed parallel concatenated code encoding, the method comprising the steps of: parsing the input data stream into a plurality of parsed data substreams; and forming sets of shared information bits, wherein each of the sets of shared information bits comprises information bits in common with respective pairs of the plurality of parsed data substreams. In a variation, a further step comprises constructing constituent permutations of one or more of the sets of shared information bits. In yet a further variation, a further step comprises interlacing respective pairs of the sets of shared information bits to form respective interleaved data substreams.
摘要翻译：一种用于交织用于解析的并行级联码编码的输入数据流的方法和装置，所述方法包括以下步骤：将所述输入数据流解析成多个解析数据子流; 以及形成共享信息比特组，其中所述共享信息比特组中的每一个包含与所述多个解析数据子流中的相应对共同的信息比特。在一个变型中，另一步骤包括构成一组或多组共享信息比特的组成置换。在又一变型中，另一步骤包括交织各组共享信息比特组以形成相应的交错数据子流。

9. 发明申请

WO2016050391A1 OPTICAL COHERENT RECEIVER WITH FORWARD ERROR CORRECTION AND PARALLEL DECODING 审中-公开
标题翻译：具有前向纠错和并行解码的光学相干接收机
公开(公告)号：WO2016050391A1
公开(公告)日：2016-04-07
申请号：PCT/EP2015/068009
申请日：2015-08-05
申请人： ALCATEL LUCENT
发明人： RAZZETTI, Luca , GAVIOLI, Giancarlo , COSTANTINI, Carlo , PEPE, Marianna
IPC分类号： H04B10/61 , H03M13/05 , H03M13/11 , H03M13/37 , H03M13/45 , H03M13/00 , H04L1/00
CPC分类号： H04L1/005 , H03M13/1111 , H03M13/1145 , H03M13/2963 , H03M13/2987 , H03M13/3746 , H03M13/6561 , H04B10/616 , H04L1/0057
摘要： It is disclosed an optical coherent receiver comprising a number of decoding blocks configured to implement iterations of a FEC iterative message-passing decoding algorithm. The decoding blocks are distributed into two (or more) parallel chains of cascaded decoding blocks. The receiver also comprises an intermediate circuit interposed between the two parallel chains. The optical coherent receiver is switchable between (i) a first operating mode, in which the intermediate circuit is inactive and the two parallel chains separately implement the FEC message-passing decoding algorithm on respective client channels; and (ii) a second operating mode, in which the intermediate circuit is active and the two parallel chains jointly implement the FEC message-passing decoding algorithm on a same client channel, by cooperating through the intermediate circuit.
摘要翻译：公开了一种光学相干接收机，其包括多个解码块，其被配置为实现FEC迭代消息传递解码算法的迭代。解码块被分配到级联解码块的两个（或多个）并行链中。接收器还包括插入在两个平行链之间的中间电路。光相干接收机可以在（i）第一操作模式之间切换，其中中间电路不活动，并且两个并行链在相应的客户信道上分别实现FEC消息传递解码算法; 以及（ii）第二操作模式，其中中间电路是有效的，并且两个并行链通过中间电路协作在同一客户信道上共同实施FEC消息传递解码算法。

10. 发明申请

WO2015000100A1 实现Turbo均衡补偿的方法以及Turbo均衡器和系统审中-公开
公开(公告)号：WO2015000100A1
公开(公告)日：2015-01-08
申请号：PCT/CN2013/078570
申请日：2013-07-01
申请人：华为技术有限公司
发明人：常德远 , 肖治宇 , 喻凡 , 赵羽
IPC分类号： H03M13/03
CPC分类号： H03M13/1154 , H03M13/2957 , H03M13/2987 , H03M13/3746 , H03M13/3972 , H03M13/616 , H03M13/6331 , H03M13/6561 , H04B10/25073 , H04B10/2543 , H04B10/2569 , H04B10/6161 , H04B10/6162 , H04L1/0045 , H04L1/0057 , H04L25/0202 , H04L25/03057 , H04L25/03171 , H04L2025/03789
摘要：本发明实施例涉及实现Turbo均衡补偿的方法以及均衡器和系统。其中，实现Turbo均衡补偿的方法包括：将第一数据块分成n个数据段，其中n个数据段中相邻的两个数据段重叠D个比特，对该n个数据段中的每一个数据段分别进行递归处理，合并经过递归处理后的n个数据段，以获得第二数据块；对第二数据块进行迭代译码，以输出第三数据块；其中第一数据块、第二数据块和第三数据块的数据长度均为LDPC卷积码的码长的1/T。本发明实施例应用于高速光纤传输系统的接收端。通过在OP-BCJR单元中对接收到的数据块采用分段处理和向前向后递归运算，以及在LDPC卷积码译码单元中对从OP-BCJR单元获取的数据进行Turbo迭代处理，能够有效提升系统吞吐量。

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