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1. 发明申请

WO2013096062A1 METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE 审中-公开
标题翻译：具有自对准源和栅格的氮化钛垂直JFET的方法和系统
公开(公告)号：WO2013096062A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/069299
申请日：2012-12-12
申请人： AVOGY, INC.
发明人： DISNEY, Donald R. , KIZILYALLI, Isik C. , NIE, Hui , ROMANO, Linda , BROWN, Richard J. , RAJ, Madhan
IPC分类号： H01L21/78
CPC分类号： H01L29/66924 , H01L21/027 , H01L21/283 , H01L21/308 , H01L29/1095 , H01L29/2003 , H01L29/402 , H01L29/66446 , H01L29/66893 , H01L29/66909 , H01L29/66916 , H01L29/7832 , H01L29/808 , H01L29/8083 , H01L29/8086
摘要： A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.
摘要翻译：半导体器件包括III族氮化物衬底，耦合到III族氮化物衬底并具有台面的第一III族氮化物外延层和耦合到台面的顶表面的第二III族氮化物外延层。半导体器件还包括耦合到台面的侧表面的III族氮化物栅极结构，以及被配置为在第二III族氮化物外延层和III族氮化物栅极结构之间提供电绝缘的间隔物。

2. 发明申请

WO2012092038A2 A METHOD TO REDUCE CONTACT RESISTANCE OF N-CHANNEL TRANSISTORS BY USING A III-V SEMICONDUCTOR INTERLAYER IN SOURCE AND DRAIN 审中-公开
标题翻译：一种通过在源极和漏极中使用III-V族半导体中间层来降低N沟道晶体管的接触电阻的方法
公开(公告)号：WO2012092038A2
公开(公告)日：2012-07-05
申请号：PCT/US2011/066271
申请日：2011-12-20
申请人： INTEL CORPORATION , MUKHERJEE, Niloy , DEWEY, Gilbert , RADOSAVLJEVIC, Marko , CHAU, Robert S. , METZ, Matthew V.
发明人： MUKHERJEE, Niloy , DEWEY, Gilbert , RADOSAVLJEVIC, Marko , CHAU, Robert S. , METZ, Matthew V.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28575 , H01L29/66446
摘要： A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.
摘要翻译：一般介绍通过在源极和漏极中使用III-V半导体中间层来减少n沟道晶体管的接触电阻的方法。就此而言，引入包括具有源极区和漏极区的n型晶体管的器件，邻近晶体管的第一层间电介质层，穿过第一层间电介质层到源极区的沟槽以及位于源极区和源极区之间的导电源触点沟槽，源极触点通过III-V半导体中间层与源极区域分开。其他实施例也被公开和要求保护。

3. 发明申请

WO2015147816A1 III-N TRANSISTORS WITH ENHANCED BREAKDOWN VOLTAGE 审中-公开
标题翻译：具有增强的断电电压的III-N晶体管
公开(公告)号：WO2015147816A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/031903
申请日：2014-03-26
申请人： INTEL CORPORATION , THEN, Han Wui , CHU-KUNG, Benjamin , DASGUPTA, Sansaptak , CHAU, Robert , SUNG, Seung Hoon , PILLARISETTY, Ravi , RADOSAVLJEVIC, Marko
发明人： THEN, Han Wui , CHU-KUNG, Benjamin , DASGUPTA, Sansaptak , CHAU, Robert , SUNG, Seung Hoon , PILLARISETTY, Ravi , RADOSAVLJEVIC, Marko
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7787 , H01L21/0254 , H01L21/02636 , H01L21/02639 , H01L21/02647 , H01L21/0332 , H01L21/8252 , H01L27/0605 , H01L29/0649 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/66431 , H01L29/66446 , H01L29/66462 , H01L29/7783 , H01L29/7786
摘要： Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.
摘要翻译：讨论了与具有增强的击穿电压的III-N型晶体管有关的技术，并结合这种晶体管的系统以及用于形成它们的方法。这种晶体管包括在衬底上具有开口的硬掩模，源极，漏极以及源极和漏极之间的沟道以及设置在硬掩模的开口上的源极或漏极的一部分。

4. 发明申请

WO2014025722A2 METHOD AND SYSTEM FOR GALLIUM NITRIDE ELECTRONIC DEVICES USING ENGINEERED SUBSTRATES 审中-公开
标题翻译：使用工程衬底的氮化镓电子器件的方法和系统
公开(公告)号：WO2014025722A2
公开(公告)日：2014-02-13
申请号：PCT/US2013/053702
申请日：2013-08-06
申请人： AVOGY, INC.
发明人： NIE, Hui , DISNEY, Donald R. , KIZILYALLI, Isik C.
IPC分类号： H01L29/80 , H01L21/20 , H01L29/20
CPC分类号： H01L21/0254 , H01L21/02645 , H01L21/6835 , H01L24/83 , H01L29/2003 , H01L29/66204 , H01L29/66212 , H01L29/66356 , H01L29/66446 , H01L29/739 , H01L29/8083 , H01L29/861 , H01L29/872 , H01L2221/68327 , H01L2224/04026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/32245 , H01L2224/83801 , H01L2224/8384 , H01L2924/12032 , H01L2924/13062 , H01L2924/00014 , H01L2924/00
摘要： A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.
摘要翻译：一种制造电子器件的方法包括提供包括III族氮化物种子层的工程化衬底结构，形成与III族氮化物种子层耦合的GaN基功能层，以及形成电耦合到至少一部分 GaN基功能层。该方法还包括将与GaN基功能层相对的载体衬底接合并去除工程衬底结构的至少一部分。该方法还包括形成电耦合到GaN基功能层的至少另一部分并去除载体衬底的第二电极结构。

5. 发明申请

WO2011021710A1 半導体素子およびその製造方法审中-公开
标题翻译：半导体元件及其生产方法
公开(公告)号：WO2011021710A1
公开(公告)日：2011-02-24
申请号：PCT/JP2010/064133
申请日：2010-08-17
申请人：株式会社パウデック , 住田行常 , 平田祥子 , 稲田隼之 , 八木修一 , 河合弘治
发明人：住田行常 , 平田祥子 , 稲田隼之 , 八木修一 , 河合弘治
IPC分类号： H01L21/205 , C30B29/38 , H01L21/336 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/12 , H01L29/47 , H01L29/78 , H01L29/872
CPC分类号： C30B29/406 , C30B25/04 , H01L21/0237 , H01L21/0254 , H01L21/02639 , H01L21/02647 , H01L29/045 , H01L29/2003 , H01L29/66446
摘要：半導体素子の製造方法は、ＧａＮ系半導体と異なる物質からなる基板上に直接または間接的に複数のストライプ状の開口を有する成長マスクを形成する工程と、この成長マスクを用いて基板上に複数の島状のＧａＮ系半導体層を（０００１）面方位に、かつＧａＮ系半導体層の〈１－１００〉方向が成長マスクのストライプ状の開口に平行な方向に延在するように成長させる工程とを有する。
摘要翻译：公开了一种半导体元件的制造方法，该半导体元件具有直接或间接地形成具有多个条纹开口的生长掩模的工艺，所述生长掩模包括不同于GaN半导体的材料的基板，以及使用生长掩模在（0001）面取向的基板上生长多个岛状GaN半导体层，使得GaN半导体层的<1-100>方向沿平行于生长面膜

6. 发明申请

WO2013020051A1 METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN CHANNEL 审中-公开
标题翻译：用于使用注册通道的GAN垂直JFET的方法和系统
公开(公告)号：WO2013020051A1
公开(公告)日：2013-02-07
申请号：PCT/US2012/049520
申请日：2012-08-03
申请人： AVOGY, INC. , KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
发明人： KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
IPC分类号： H01L29/772
CPC分类号： H01L29/66909 , H01L21/8252 , H01L27/0605 , H01L29/1066 , H01L29/2003 , H01L29/66446 , H01L29/66924 , H01L29/8083
摘要： A vertical Ill-nitride field effect transistor includes a drain comprising a first Ill-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second Ill-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third Ill-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical Ill-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region.
摘要翻译：垂直III族氮化物场效应晶体管包括：包括第一III族氮化物材料的漏极，与漏极电耦合的漏极接触点，以及包括耦合到漏极的第二III族氮化物材料的漂移区域。场效应晶体管还包括沟道区，该沟道区包括耦合到漏极并沿着垂直方向邻近漏极设置的第三III族氮化物材料，至少部分围绕沟道区的栅极区。场效应晶体管还包括耦合到沟道区的源极和电耦合到源极的源极接触。沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直的氮化物场效应晶体管的工作期间的电流沿着垂直方向，并且沟道区沿第二表面的至少一部分延伸的门区域。

7. 发明申请

WO2012105611A1 半導体パワーデバイスおよびその製造方法审中-公开
标题翻译：半导体电源装置及其制造方法
公开(公告)号：WO2012105611A1
公开(公告)日：2012-08-09
申请号：PCT/JP2012/052290
申请日：2012-02-01
申请人：ローム株式会社 , 中野佑紀
发明人：中野　佑紀
IPC分类号： H01L29/47 , H01L21/283 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/872
CPC分类号： H01L21/049 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02241 , H01L21/02255 , H01L21/02271 , H01L21/044 , H01L21/28008 , H01L21/28264 , H01L27/04 , H01L29/0619 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/4236 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66045 , H01L29/6606 , H01L29/66068 , H01L29/66446 , H01L29/8611 , H01L29/872 , H01L2224/0603
摘要：　本発明の半導体パワーデバイスは、第１電極および第２電極と、所定の厚さおよび不純物濃度を有する半導体からなり、前記第１電極および前記第２電極が接合され、当該第１電極と第２電極との間に電気伝導を発生させるキャリヤが移動するための活性領域を有する耐圧保持層と、前記耐圧保持層上に形成され、前記耐圧保持層に接する部分に、ＳｉＯ２よりも高い誘電率を有する高誘電率部を有する絶縁膜とを含む。
摘要翻译：该半导体功率器件包括：第一电极和第二电极; 包含具有规定厚度和杂质浓度的半导体的击穿电压维持层被接合到第一电极和第二电极，并且具有用于容纳用于在第一电极和第二电极之间产生导电性的载体的移动的有源区域第二电极; 以及形成在击穿电压维持层上的绝缘膜，并且在与击穿电压维持层接触的部分中具有比SiO 2更高的介电常数的高介电常数部分。

8. 发明申请

WO2004010489A1 縦型接合型電界効果トランジスタ、及び縦型接合型電界効果トランジスタの製造方法审中-公开
标题翻译：垂直连接场效应晶体管及其制造方法
公开(公告)号：WO2004010489A1
公开(公告)日：2004-01-29
申请号：PCT/JP2003/009412
申请日：2003-07-24
申请人：住友電気工業株式会社 , 星野孝志 , 原田真 , 藤川一洋 , 初川聡 , 弘津研一
发明人：星野孝志 , 原田真 , 藤川一洋 , 初川聡 , 弘津研一
IPC分类号： H01L21/337
CPC分类号： H01L29/66068 , H01L29/0634 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/66446 , H01L29/66909 , H01L29/8083
摘要： A vertical JFET (1a) comprising an n-type drain semiconductor part (2), an n-type drift semiconductor part (3), a p -type gate semiconductor part (4), an n-type channel semiconductor part (5), an n -type source semiconductor part (7), and a p -type gate semiconductor part (8). The n-type drift semiconductor part (3) is provided on the major surface of the n-type drain semiconductor part (2) and has first through fourth regions (3a-3d) extending in the direction intersecting the major surface. The p -type gate semiconductor part (4) is provided on the first through third regions (3a-3c) of the n-type drift semiconductor part (3). The n-type channel semiconductor part (5) is provided along the p -type gate semiconductor part (4) and connected electrically with the fourth region (3d) of the n-type drift semiconductor part (3).
摘要翻译：包括n型漏极半导体部分（2），n型漂移半导体部分（3），ap +型栅极半导体部分（4），n型沟道半导体部分（4）的垂直JFET（1a） 5），n +型源极半导体部（7）和ap +型栅极半导体部（8）。 n型漂移半导体部件（3）设置在n型漏极半导体部件（2）的主表面上，并且具有沿与主表面相交的方向延伸的第一至第四区域（3a-3d）。 p +型栅极半导体部件（4）设置在n型漂移半导体部件（3）的第一至第三区域（3a-3c）上。 n型沟道半导体部件（5）沿着p +型栅极半导体部件（4）设置并与n型漂移半导体部件（3）的第四区域（3d）电连接。

9. 发明申请

WO01080294A2 MOCVD-GROWN EMODE HIGFET BUFFER 审中-公开
公开(公告)号：WO01080294A2
公开(公告)日：2001-10-25
申请号：PCT/US2001/008285
申请日：2001-03-15
IPC分类号： H01L21/205 , H01L21/335
CPC分类号： H01L29/66446 , H01L21/02395 , H01L21/02463 , H01L21/02502 , H01L21/02546 , Y10S438/93
摘要： A method of fabricating an Emode HIGFET semiconductor device (50), and the device, is disclosed including epitaxially growing by metal-organic chemical vapor deposition an epitaxial buffer (11). The buffer(11) includes a layer of short-lifetime gallium arsenide (14) on a gallium arsenide substrate (12) and a layer of aluminum gallium arsenide (15) on the layer of short-lifetime gallium arsenide (14). The short-lifetime gallium arsenide (14) is grown at a temperature below approximately 550 DEG C so as to have a lifetime less than approximately 500 picoseconds. A stack of compound semiconductor layers (10) is then epitaxially grown on the layer of aluminum gallium arsenide (15) of the buffer and an Emode field effect transistor (50) is formed in the stack.
摘要翻译：公开了一种制造Emode HIGFET半导体器件（50）的方法和该器件，其包括通过金属 - 有机化学气相沉积外延生长外延缓冲器（11）。缓冲器（11）包括在砷化镓衬底（12）上的短寿命砷化镓（14）层和在短寿命砷化镓（14）层上的砷化铝砷化镓层（15）。短寿命的砷化镓（14）在低于约550℃的温度下生长，使其寿命小于约500皮秒。然后在缓冲器的砷化镓（15）层上外延生长堆叠的化合物半导体层（10），并且在堆叠中形成发光二极管场效应晶体管（50）。

10. 发明申请

WO1989005040A1 QUANTUM WELL FIELD-CONTROLLED SEMICONDUCTOR TRIODE 审中-公开
标题翻译：量子阱场控制半导体三极管
公开(公告)号：WO1989005040A1
公开(公告)日：1989-06-01
申请号：PCT/US1988003850
申请日：1988-10-31
申请人： BELL COMMUNICATIONS RESEARCH, INC.
发明人： BELL COMMUNICATIONS RESEARCH, INC. , GRINBERG, Anatoly , KASTALSKY, Alexander
IPC分类号： H01L29/76
CPC分类号： H01L29/66446 , H01L29/1029 , H01L29/452 , H01L29/475 , H01L29/772 , H01L29/7783
摘要： A semiconductor device formed on a substrate (10) includes a first layer (11) of semiconductor material of a first conductivity type forming a collector (drain) region of said device; and a second layer (12) of semiconductor material of a first conductivity type composed of a relatively wide energy bandgap material disposed on the first layer (11) and forming a collector potential barrier region of the device. A third layer (15) of semiconductor material is provided composed of a relatively narrow energy bandgap material disposed on the second layer (12) and forming an emitter (source) region of the device. A fourth layer (16) of semiconductor material is further provided composed of a relatively wide energy bandgap material disposed on the third layer (15) and forming a gate region of the device. Carriers are confined in layer (15) which forms a double barrier single quantum well structure together with layers (12, 16). A Ti/AuGe/Au metallization is used for making a vertical ohmic contact to the collector region (11), a selective lateral contact to the quantum well region (15) and a Schottky contact to the gate region (16). In operation, the gate structure (16, 17, 18, 22) controls the variation of the work function for thermionic emission from the quantum well region (15) to the collector region (11) over the collector potential barrier region (12). In order to minimize a current leakage to the gate, the gate barrier in the quantum well is preferably larger than the collector barrier.

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