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1. 发明申请

WO2013096062A1 METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE 审中-公开
标题翻译：具有自对准源和栅格的氮化钛垂直JFET的方法和系统
公开(公告)号：WO2013096062A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/069299
申请日：2012-12-12
申请人： AVOGY, INC.
发明人： DISNEY, Donald R. , KIZILYALLI, Isik C. , NIE, Hui , ROMANO, Linda , BROWN, Richard J. , RAJ, Madhan
IPC分类号： H01L21/78
CPC分类号： H01L29/66924 , H01L21/027 , H01L21/283 , H01L21/308 , H01L29/1095 , H01L29/2003 , H01L29/402 , H01L29/66446 , H01L29/66893 , H01L29/66909 , H01L29/66916 , H01L29/7832 , H01L29/808 , H01L29/8083 , H01L29/8086
摘要： A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.
摘要翻译：半导体器件包括III族氮化物衬底，耦合到III族氮化物衬底并具有台面的第一III族氮化物外延层和耦合到台面的顶表面的第二III族氮化物外延层。半导体器件还包括耦合到台面的侧表面的III族氮化物栅极结构，以及被配置为在第二III族氮化物外延层和III族氮化物栅极结构之间提供电绝缘的间隔物。

2. 发明申请

WO2014025722A2 METHOD AND SYSTEM FOR GALLIUM NITRIDE ELECTRONIC DEVICES USING ENGINEERED SUBSTRATES 审中-公开
标题翻译：使用工程衬底的氮化镓电子器件的方法和系统
公开(公告)号：WO2014025722A2
公开(公告)日：2014-02-13
申请号：PCT/US2013/053702
申请日：2013-08-06
申请人： AVOGY, INC.
发明人： NIE, Hui , DISNEY, Donald R. , KIZILYALLI, Isik C.
IPC分类号： H01L29/80 , H01L21/20 , H01L29/20
CPC分类号： H01L21/0254 , H01L21/02645 , H01L21/6835 , H01L24/83 , H01L29/2003 , H01L29/66204 , H01L29/66212 , H01L29/66356 , H01L29/66446 , H01L29/739 , H01L29/8083 , H01L29/861 , H01L29/872 , H01L2221/68327 , H01L2224/04026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/32245 , H01L2224/83801 , H01L2224/8384 , H01L2924/12032 , H01L2924/13062 , H01L2924/00014 , H01L2924/00
摘要： A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.
摘要翻译：一种制造电子器件的方法包括提供包括III族氮化物种子层的工程化衬底结构，形成与III族氮化物种子层耦合的GaN基功能层，以及形成电耦合到至少一部分 GaN基功能层。该方法还包括将与GaN基功能层相对的载体衬底接合并去除工程衬底结构的至少一部分。该方法还包括形成电耦合到GaN基功能层的至少另一部分并去除载体衬底的第二电极结构。

3. 发明申请

WO2013085748A1 VERTICAL GaN JFET WITH GATE AND SOURCE ELECTRODES ON REGROWN GATE 审中-公开
标题翻译：具有门和源电极的垂直GaN JFET在注册门上
公开(公告)号：WO2013085748A1
公开(公告)日：2013-06-13
申请号：PCT/US2012/066669
申请日：2012-11-27
申请人： AVOGY, INC.
发明人： DISNEY, Donald R. , NIE, Hui , KIZILYALLI, Isik C. , BROWN, Richard J.
IPC分类号： H01L29/732 , H01L29/739
CPC分类号： H01L29/8083 , H01L29/0623 , H01L29/2003 , H01L29/402 , H01L29/66446 , H01L29/66462 , H01L29/66909 , H01L29/66924
摘要： A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.
摘要翻译：半导体结构包括具有第一表面和第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。第一电极电耦合到GaN衬底的第二表面。半导体结构还包括耦合到GaN衬底的第一表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN层。第一GaN外延层包括沟道区。第二GaN外延层包括栅极区域和边缘端接结构。耦合到栅极区域的第二电极和耦合到沟道区域的第三电极都设置在边缘端接结构内。

4. 发明申请

WO2013074291A1 METHOD AND SYSTEM FABRICATING FLOATING GUARD RINGS IN GAN MATERIALS 审中-公开
标题翻译：方法和系统制作烟草材料中的浮动保护环
公开(公告)号：WO2013074291A1
公开(公告)日：2013-05-23
申请号：PCT/US2012/062717
申请日：2012-10-31
申请人： AVOGY, INC.
发明人： DISNEY, Donald R. , EDWARDS, Andrew P. , NIE, Hui , BROWN, Richard J. , KIZILYALLI, Isik C. , BOUR, David P. , ROMANO, Linda , PRUNTY, Thomas R.
IPC分类号： H01L29/06
CPC分类号： H01L21/761 , H01L21/2654 , H01L21/266 , H01L21/765 , H01L29/0619 , H01L29/0642 , H01L29/0692 , H01L29/2003 , H01L29/402 , H01L29/66136 , H01L29/66212 , H01L29/6631 , H01L29/66909 , H01L29/8083 , H01L29/872
摘要： A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.
摘要翻译：一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二与第一导电类型相反的第二导电类型的GaN外延层。第二GaN外延层耦合到第一GaN外延层。该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

5. 发明申请

WO2014107304A1 GALLIUM NITRIDE VERTICAL JFET WITH HEXAGONAL CELL STRUCTURE 审中-公开
标题翻译：具有六角形细胞结构的硝酸锌垂直JFET
公开(公告)号：WO2014107304A1
公开(公告)日：2014-07-10
申请号：PCT/US2013/076007
申请日：2013-12-18
申请人： AVOGY, INC.
发明人： EDWARDS, Andrew P. , NIE, Hui , DISNEY, Donald R. , KIZILYALLI, Isik
IPC分类号： H01L29/15
CPC分类号： H01L27/098 , H01L29/0692 , H01L29/2003 , H01L29/42312 , H01L29/66909 , H01L29/8083
摘要： An array of GaN-based vertical JFETs includes a GaN substrate comprising a drain of one or more of the JFETs and one or more epitaxial layers coupled to the GaN substrate. The array also includes a plurality of hexagonal cells coupled to the one or more epitaxial layers and extending in a direction normal to the GaN substrate. Sidewalls of the plurality of hexagonal cells are substantially aligned with respect to crystal planes of the GaN substrate. The array further includes a plurality of channel regions, each having a portion adjacent a sidewall of the plurality of hexagonal cells, a plurality of gate regions of one or more of the JFETs, each electrically coupled to one or more of the plurality of channel regions, and a plurality of source regions of one or more of the JFETs electrically coupled to one or more of the plurality of channel regions.
摘要翻译： GaN基垂直JFET的阵列包括包含一个或多个JFET的漏极和耦合到GaN衬底的一个或多个外延层的GaN衬底。该阵列还包括耦合到一个或多个外延层并沿垂直于GaN衬底的方向延伸的多个六边形单元。多个六边形单元的侧壁相对于GaN衬底的晶面基本上对齐。阵列还包括多个通道区域，每个沟道区域具有邻近多个六边形单元的侧壁的部分，一个或多个JFET的多个栅极区域，每个栅极区域电耦合到多个沟道区域中的一个或多个以及电耦合到多个沟道区中的一个或多个的一个或多个JFET的多个源极区。

6. 发明申请

WO2013096013A1 METHOD OF FABRICATING A GALLIUM NITRIDE P-I-N DIODE USING IMPLANTATION 审中-公开
标题翻译：使用植入制备氮化镓P-I-N二极体的方法
公开(公告)号：WO2013096013A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/068972
申请日：2012-12-11
申请人： AVOGY, INC.
发明人： KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , BROWN, Richard J. , DISNEY, Donald R.
IPC分类号： H01L31/112
CPC分类号： H01L29/868 , H01L29/0615 , H01L29/0649 , H01L29/2003 , H01L29/66204 , H01L29/66212 , H01L29/6631 , H01L29/66924
摘要： A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region
摘要翻译： III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区，并且包括包含第一III族氮化物外延材料的一部分的注入区。第一III族氮化物外延材料的注入区域相对于邻近于注入区域的第一III族氮化物外延材料的部分具有降低的导电性

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