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1. 发明申请

WO2016105393A1 GENERIC QUEUE 审中-公开
标题翻译：一般队伍
公开(公告)号：WO2016105393A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072203
申请日：2014-12-23
申请人： INTEL CORPORATION
发明人： CHENG, Albert S. , PARKER, Michael A. , LOVETT, Thomas D. , HOOVER, Steven F.
IPC分类号： H04L12/861
CPC分类号： H04L49/9036 , H04L47/6205 , H04L47/621 , H04L49/3027
摘要： Apparatuses, methods and storage medium associated with the placement of data packets in one or more queues of a switch are described herein. In embodiments, the switch may include a plurality of virtual lane (VL) queues (VLQs) and a plurality of generic queues (GQs). A queue manager may be configured to selectively place a packet of a particular VL in a corresponding VLQ or a GQ. Other embodiments may be described and/or claimed.
摘要翻译：这里描述了与交换机的一个或多个队列中的数据分组的放置相关联的装置，方法和存储介质。在实施例中，交换机可以包括多个虚拟通道（VL）队列（VLQ）和多个通用队列（GQ））。队列管理器可以被配置为选择性地将特定VL的分组放置在相应的VLQ或GQ中。可以描述和/或要求保护其他实施例。

2. 发明申请

WO2011100878A1 交换网流控实现方法、交换设备及系统审中-公开
公开(公告)号：WO2011100878A1
公开(公告)日：2011-08-25
申请号：PCT/CN2010/076746
申请日：2010-09-09
申请人：华为技术有限公司 , 孙团会 , 李德丰 , 苏皓 , 曹爱娟 , 宋健
发明人：孙团会 , 李德丰 , 苏皓 , 曹爱娟 , 宋健
IPC分类号： H04L12/56
CPC分类号： H04L47/12 , H04L47/26 , H04L49/3027 , H04L49/506 , H04L49/552

3. 发明申请

WO2009050501A2 DATA SWITCH 审中-公开
标题翻译：数据开关
公开(公告)号：WO2009050501A2
公开(公告)日：2009-04-23
申请号：PCT/GB2008/050907
申请日：2008-10-06
申请人： VIRTENSYS LIMITED , NAVEN, Finbar , DREWRY, John Roger
发明人： NAVEN, Finbar , DREWRY, John Roger
IPC分类号： H04L25/08
CPC分类号： H04J3/0685 , H04L49/3018 , H04L49/3027 , H04L49/90 , H04L49/901 , H04L2012/5674
摘要： A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulatedspread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.
摘要翻译：一种用于集成电路的数据开关，包括用于从具有预定扩频链路时钟频率特性的独立调制的扩展频谱时钟（SSC）使能源接收输入数据分组的至少一个链路，以及用于在通过后发送数据分组的至少一个输出所述交换机还包括至少一个具有链路侧和核心侧的接收缓冲器，用于从所述链路，至少一个发射缓冲器和核心时钟接收SSC调制的输入数据分组，其中所述核心时钟在给定的频率在由单独的振荡精度确定的预定误差极限之间并且不是SSC使能，核心时钟频率被设置在至少与最高链路时钟频率一样高的水平，使得接收缓冲器不能从其链路侧更快地被填充它可以从其核心方面清空。

4. 发明申请

WO2007015820A1 EFFICIENT MESSAGE SWITCHING IN A SWITCHING APPARATUS 审中-公开
标题翻译：切换设备中的高效消息切换
公开(公告)号：WO2007015820A1
公开(公告)日：2007-02-08
申请号：PCT/US2006/027729
申请日：2006-07-18
申请人： ENIGMA SEMICONDUCTOR, INC. , NIELSEN, Jacob, V.
发明人： NIELSEN, Jacob, V.
IPC分类号： H04L12/56
CPC分类号： H04L49/608 , H04L47/50 , H04L47/522 , H04L47/6225 , H04L49/101 , H04L49/3018 , H04L49/3027 , H04L49/3072 , H04L49/503 , H04L2012/5679
摘要： A system and method of transferring packets/cells and messages within a switching apparatus that includes a plurality of input units (100, 192) , a packet/cell switch element (160) , a message controller (130) , and a plurality of output units (190, 194) . It is identified as to whether or not an item to be transferred from one of the input units or output units to another of the input units or output units is a message or a packet/cell. If the item to be transferred is a packet/cell (150, 152) , the packet/cell is transferred from one of the input units to one of the output units using links dedicated for packet/cell transfer (140, 170) and a packet/cell switch element. If the item to be transferred is a message (120) , the message is transferred from one of the input units or output units to another of the input units or output units using links dedicated for message transfer (110) and a message controller.
摘要翻译：一种在包括多个输入单元（100,192），分组/小区开关元件（160），消息控制器（130）和多个输出的交换设备内传送分组/小区和消息的系统和方法单位（190，194）。确定要从输入单元或输出单元之一转移到另一输入单元或输出单元的项是否是消息或分组/单元。如果要传送的项目是分组/小区（150,152），则使用专用于分组/小区传输（140,170）的链路和分组/小区传送（140,170）的分组/小区从一个输入单元传送到一个输出单元分组/小区切换元素。如果要传送的项目是消息（120），则使用专用于消息传送的链接（110）和消息控制器将消息从输入单元或输出单元之一传送到另一个输入单元或输出单元。

5. 发明申请

WO2006019867A3 A DUAL-SCALER ARCHITECTURE FOR REDUCING VIDEO PROCESSING REQUIREMENTS 审中-公开
标题翻译：用于减少视频处理要求的双扩展器架构
公开(公告)号：WO2006019867A3
公开(公告)日：2006-06-08
申请号：PCT/US2005024928
申请日：2005-07-15
申请人： GREENFOREST CONSULTING INC , LOUIE JAMES YAT , SHYU MENQ YU
发明人： LOUIE JAMES YAT , SHYU MENQ YU
IPC分类号： H04N7/01
CPC分类号： H04N7/01 , G06T3/4023 , G09G5/005 , G09G5/008 , G09G5/18 , G09G2300/0408 , G09G2310/0229 , G09G2340/0414 , G09G2340/0421 , G09G2340/0435 , G09G2340/0442 , H03L7/1976 , H04L49/10 , H04L49/30 , H04L49/3018 , H04L49/3027 , H04N5/14 , H04N5/46 , H04N7/012 , H04N21/42692 , H04N21/440218
摘要： A video signal processor (300) includes an input port to receive an input video signal. The input video signal is having a first horizontal resolution and a first vertical resolution. The video signal processor (300) also includes a prescaler (310) to prescale the video signal, wherein prescaling (412) converts the input video signal at the first horizontal resolution and first vertical resolution to a prescaled video signal having a second horizontal resolution and a second vertical resolution. The video signal processor (300) additionally includes a frame buffer (314) coupled to the prescaler (310). The video signal processor (300) includes a horizontal scaler (318) to convert (224) the horizontal scale of the prescaled video signal from the second horizontal resolution to a third horizontal resolution and a vertical scaler (318) to convert (226) the vertical scale of the prescaled video signal from the second vertical resolution to a third vertical resolution.
摘要翻译：视频信号处理器（300）包括用于接收输入视频信号的输入端口。输入视频信号具有第一水平分辨率和第一垂直分辨率。视频信号处理器（300）还包括预分频器（310），用于对视频信号进行预分频，其中预分频（412）将具有第一水平分辨率和第一垂直分辨率的输入视频信号转换成具有第二水平分辨率的预分频视频信号，第二垂直分辨率。视频信号处理器（300）还包括耦合到预分频器（310）的帧缓冲器（314）。视频信号处理器（300）包括水平缩放器（318），用于将预定视频信号的水平尺度从第二水平分辨率转换（224）到第三水平分辨率（318），以转换（226）从第二垂直分辨率到第三垂直分辨率的预分视频信号的垂直比例。

6. 发明申请

WO2006019867A2 A DUAL-SCALER ARCHITECTURE FOR REDUCING VIDEO PROCESSING REQUIREMENTS 审中-公开
标题翻译：用于减少视频处理要求的双扩展器架构
公开(公告)号：WO2006019867A2
公开(公告)日：2006-02-23
申请号：PCT/US2005/024928
申请日：2005-07-15
申请人： GREENFOREST CONSULTING, INC. , LOUIE, James Yat , SHYU, Menq Yu
发明人： LOUIE, James Yat , SHYU, Menq Yu
IPC分类号： H04N9/74
CPC分类号： H04N7/01 , G06T3/4023 , G09G5/005 , G09G5/008 , G09G5/18 , G09G2300/0408 , G09G2310/0229 , G09G2340/0414 , G09G2340/0421 , G09G2340/0435 , G09G2340/0442 , H03L7/1976 , H04L49/10 , H04L49/30 , H04L49/3018 , H04L49/3027 , H04N5/14 , H04N5/46 , H04N7/012 , H04N21/42692 , H04N21/440218
摘要： A video signal processor includes an input port adapted to receive an input video signal. The input video signal is characterized by a first horizontal resolution and a first vertical resolution. The video signal processor also includes a prescaler adapted to perform prescaling of the video signal, wherein prescaling converts the input video signal at the first horizontal resolution and the first vertical resolution to a prescaled video signal characterized by a second horizontal resolution and a second vertical resolution. The video signal processor additionally includes a frame buffer coupled to the prescaler. The video signal processor further includes a horizontal scaler adapted to convert the horizontal scale of the prescaled video signal from the second horizontal resolution to a third horizontal resolution and a vertical scaler adapted to convert the vertical scale of the prescaled video signal from the second vertical resolution to a third vertical resolution.
摘要翻译：视频信号处理器包括适于接收输入视频信号的输入端口。输入视频信号的特征在于第一水平分辨率和第一垂直分辨率。视频信号处理器还包括预分频器，其适于执行视频信号的预分频，其中预分频将第一水平分辨率和第一垂直分辨率的输入视频信号转换为预分频视频信号，其特征在于第二水平分辨率和第二垂直分辨率。视频信号处理器还包括耦合到预分频器的帧缓冲器。视频信号处理器还包括水平缩放器，其适于将预定视频信号的水平尺度从第二水平分辨率转换为第三水平分辨率;以及垂直缩放器，适于将预分频视频信号的垂直比例从第二垂直分辨率到第三垂直分辨率。

7. 发明申请

WO2005107192A1 SYSTEM AND METHOD FOR ENHANCING NETWORK QUALITY OF SERVICE 审中-公开
标题翻译：提高网络质量服务质量的系统和方法
公开(公告)号：WO2005107192A1
公开(公告)日：2005-11-10
申请号：PCT/US2005/014567
申请日：2005-04-27
申请人： THOMSON LICENSING S.A. , STAHL, Thomas, Anthony
发明人： STAHL, Thomas, Anthony
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L41/00 , H04L47/12 , H04L47/20 , H04L49/205 , H04L49/3027 , H04L49/3054 , H04L49/351
摘要： A data transfer network infrastructure device having a plurality of ingress ports for accepting data from a domain of a data network; and, a user interface for enabling a user to limit a rate at which data is accepted from the data network on at least one of the ingress ports, wherein the data transfer rate between the at least one of the ingress ports and a device coupled to the at least one of the ports is limited, whereby a bandwidth limit is implemented by the limit at which the data is accepted into the ingress port.
摘要翻译：一种具有多个入口端口的数据传输网络基础设施设备，用于接收来自数据网络域的数据; 以及用户界面，用于使得用户能够在至少一个入口端口上限制从数据网络接收数据的速率，其中至少一个入口端口与耦合到端口中的至少一个被限制，由此通过数据被接收到入口端口的限制来实现带宽限制。

8. 发明申请

WO2005086791A2 HIGHLY PARALLEL SWITCHING SYSTEMS UTILIZING ERROR CORRECTION II 审中-公开
标题翻译：使用错误校正的高并行切换系统II
公开(公告)号：WO2005086791A2
公开(公告)日：2005-09-22
申请号：PCT/US2005/007488
申请日：2005-03-08
申请人： INTERACTIC HOLDINGS, LLC , REED, Coke , MURPHY, David
发明人： REED, Coke , MURPHY, David
IPC分类号： H04L12/56 , H04Q3/68
CPC分类号： H04Q3/68 , H04L12/18 , H04L49/101 , H04L49/15 , H04L49/1523 , H04L49/201 , H04L49/254 , H04L49/3027 , H04L49/45 , H04L49/557 , H04L49/602
摘要： An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage network. The first and second stage networks each have more outputs than inputs. The data is first sent from the first device to the first stage network and then from the first stage network to the second stage network. The data is sent to the second device from the second stage network. The number of inputs to a device w the collection of devices from the second stage network exceeds the number of outputs from device w into the first stage network. The device w with N p input ports is capable of simultaneously receiving data from N p devices in the collection of devices. The latency through the entire system may be a fixed constant.
摘要翻译：互连网络具有第一级网络和第二级网络以及网络外的设备集合，使得第一设备能够将数据发送到第二设备。第一级网络连接到第二级网络的输入。第一和第二级网络每个都具有比输入更多的输出。数据首先从第一设备发送到第一级网络，然后从第一级网络发送到第二级网络。数据从第二级网络发送到第二设备。来自第二级网络的设备的收集的设备的输入数量超过从设备w进入第一级网络的输出的数量。具有Np输入端口的设备w能够同时从设备集合中的Np设备接收数据。整个系统的延迟可能是一个固定的常数。

9. 发明申请

WO2005048501A2 NONBLOCKING AND DETERMINISTIC MULTIRATE MULTICAST PACKET SCHEDULING 审中-公开
标题翻译：非限制性和决定性多媒体分组调度
公开(公告)号：WO2005048501A2
公开(公告)日：2005-05-26
申请号：PCT/US2004/036052
申请日：2004-10-29
申请人： KONDA, Venkat
发明人： KONDA, Venkat
IPC分类号： H04L
CPC分类号： H04L47/10 , H04L45/00 , H04L47/125 , H04L47/15 , H04L47/50 , H04L47/521 , H04L49/1523 , H04L49/201 , H04L49/254 , H04L49/3018 , H04L49/3027
摘要： A system for scheduling multirate multicast packets with rate weight through an interconnection network, comprising r 1 input ports with each input port having r 2 input queues, r 2 output ports with each output port having r 1 , output queues, and the interconnection network having a speedup of at least (Ι) with s subnetworks, and each subnetwork comprising at least one first internal link connected to each input, port for a total of at least r 1 first internal links, each subnetwork further comprising at least one second internal link connected to each output port for a total of at least r 2 second internal links is operated in strictly nonblocking manner in accordance with the invention by scheduling corresponding to the packet-rate weight, at most r 1 packets in each switching time to be switched in at most r 2 switching times when r 1 , ≤ r 2 , and at most r 2 packets in each switching time to be switched in at most r 1 , switching times when r 2 ≤ r 1 , in deterministic manner and without the requirement of segmentation and reassembly of packets. The scheduling is performed so that each multicast packet is . fan-out split through not more, than two interconnection networks, and not more than two switching times. The system is also operated at 100% throughput, work conserving, fair, and yet deterministically thereby never congesting the output ports. The system performs only one iteration for arbitration, and with mathematical minimum speedup in the interconnection network. The system operates with absolutely no packet reordering issues, no internal buffering of packets in the interconnection network, and hence in a truly cut-through and distributed manner. In one embodiment, the speedup is implemented with only one subnetwork and with triple switching rate through the subnetwork. In another embodiment, the system is operated in rearrangeably nonblocking manner with a speedup of at least (ΙΙ) in the interconnection network. When the number of input ports r 1 , is equal to the number of output ports r 2 , and r 1 , = r 2 = r , the interconnection network having a speedup of at least (ΙΙΙ), is operated in strictly nonblocking and, deterministic manner in accordance with the invention by scheduling corresponding to the packet rate weight, at most r packets in each switching time to be switched in at most r switching times. And with a speedup of at least (ΙV) in the interconnection network, the system is operated in J rearrangeably nonblocking and deterministic manner. The system also offers end to end guaranteed bandwidth and latency for miltirate multicast packets.from input ports to output ports. In all the embodiments, the interconnection network may be crossbar network, shared memory network, clos network, hypercube network, or any internally nonblocking interconnection network or network of networks.
摘要翻译：一种用于通过互连网络调度具有速率权重的多速率多播分组的系统，包括具有每个输入端口具有r2个输入队列的r1个输入端口，每个输出端口具有r1的输出端口，输出队列，以及具有加速的互连网络至少（Iota）具有子网络，并且每个子网络包括连接到每个输入的至少一个第一内部链路，用于总共至少r1个第一内部链路的端口，每个子网络还包括连接到每个输出端口的至少一个第二内部链路总共至少r2个第二内部链路根据本发明通过对应于分组速率权重的调度以严格的非阻塞方式操作，每个切换时间中最多r1个分组在最多r2个切换时间切换，当r1 ，<= r2，并且在每个切换时间中最多r2个分组最多切换到r1，r2 <= r1的切换时间，以确定的方式并且没有r 数据包的分段和重组的设计。执行调度以使得每个组播分组是。扇出分裂不超过两个互连网络，并且不超过两个切换时间。该系统还以100％吞吐量，工作节省，公平和确定性运行，从而不会使输出端口堵塞。系统仅执行一次迭代进行仲裁，并在互连网络中进行数学最小加速。该系统绝对没有任何数据包重新排序问题，互连网络中的数据包没有内部缓冲，因此以真正的直通和分布式方式运行。在一个实施例中，加速仅通过一个子网实现，并且通过子网实现三重切换速率。在另一个实施例中，系统以可重新排列的非阻塞方式操作，并且在互连网络中加速至少（IotaI）。当输入端口r1的数量等于输出端口r2的数量，并且r1 = r2 = r时，具有至少（IotaIota）的加速的互连网络按照严格的非阻塞和确定的方式按照通过本发明通过对应于分组速率权重的调度，在每个切换时间中最多r个分组被切换到最多r个切换时间。并且在互连网络中加速至少（IotaV），系统以J可重新排列的非阻塞和确定性方式运行。该系统还提供从输入端口到输出端口的端到端保证带宽和延迟。在所有实施例中，互连网络可以是交叉网络，共享存储器网络，闭路网络，超立方体网络或任何内部非阻塞互连网络或网络网络。

10. 发明申请

WO2005045633A2 NONBLOCKING AND DETERMINISTIC UNICAST PACKET SCHEDULING 审中-公开
标题翻译：非限制性和确定性的UNICAST包装调度
公开(公告)号：WO2005045633A2
公开(公告)日：2005-05-19
申请号：PCT/US2004/035954
申请日：2004-10-29
申请人： KONDA, Venkat
发明人： KONDA, Venkat
IPC分类号： G06F
CPC分类号： H04L47/52 , H04L47/50 , H04L49/10 , H04L49/3018 , H04L49/3027
摘要： A system for scheduling unicast packets through an interconnection network, comprising r 1 , input ports with each input port having r 2 input queues, r 2 output ports with each output port having r 1 output queues, and the interconnection network having a speedup of at least with, Formula (I), subnetworks, and each subnetwork comprising at least one first internal link connected to each input port for a total of at least r 1 first internal links, each subnetwork further comprising at least one second internal link connected to each output port for a total of at least r 2 second internal links is operated in strictly nonblocking manner in accordance with the invention by scheduling, at most r 1 packets in each switching time to be switched in at most r 1 switching times when r 1 ≤ r 2 and at most r 2 packets in each switching time to be switched in at most r 1 switching times when r 2 ≤ r 1 in deterministic manner, and without the requirement of segmentation and reassembly of packets. The system is also operated at 100% throughput, work conserving, fair, and yet deterministically thereby never congesting the output ports. The system performs only one iteration for arbitration, and with mathematical minimum speedup in the interconnection network. The system operates with absolutely no packet reordering issues, no internal buffering of packets in the interconnection network, and hence in a truly cut-through and distributed manner. In one embodiment, the system is operated in strictly nonblocking manner with only one subnetwork and with double switching rate through the subnetwork. In another embodiment, the system is operated in rearrangeably nonblocking manner with a speedup of at least, Formula (II), in the interconnection network. When the number of input ports r 1 is equal to the number of output ports Pi, and r 1 = r 2 = r , the interconnection network having a speedup of at least, Formula (III), is operated in strictly nonblocking and deterministic manner in accordance with the invention by scheduling at most r packets in each switching time to be switched in at most r switching times. And with a speedup of at least, Formula (IV), in the interconnection network, the system is operated in rear rangeably nonblocking and deterministic manner. The system also offers end to end guaranteed bandwidth and latency for packets from input ports to output ports. In all the embodiments, the interconnection network may be crossbar network, shared memory network, clos network, hypercube network, or any internally nonblocking interconnection network or network of networks.
摘要翻译：一种用于通过互连网络调度单播数据包的系统，包括r1，具有每个输入端口具有r2个输入队列的输入端口，每个输出端口具有r1个输出队列的r2个输出端口，以及至少具有加速度的互连网络（I），子网络和每个子网络包括连接到每个输入端口的至少一个第一内部链路，用于总共至少r1个第一内部链路，每个子网络还包括连接到每个输出端口的至少一个第二内部链路，用于总计至少r2个第二内部链路按照本发明通过调度以严格的非阻塞方式操作，每个切换时间中最多r1个分组在r1 <= r2和每个最多r2个分组中最多r1个切换时间切换当确定性方式r2 <= R1时，切换时间最多为r1个切换时间，无需分组和重组。该系统还以100％吞吐量，工作节省，公平和确定性运行，从而不会使输出端口堵塞。系统仅执行一次迭代进行仲裁，并在互连网络中进行数学最小加速。该系统绝对没有任何数据包重新排序问题，互连网络中的数据包没有内部缓冲，因此以真正的直通和分布式方式运行。在一个实施例中，系统以严格的非阻塞方式仅运行一个子网络，并且通过子网络具有双重切换速率。在另一个实施例中，在互连网络中，以可重新排列的非阻塞方式操作系统至少具有公式（II）的加速。当输入端口r1的数量等于输出端口Pi的数量，并且r1 = r2 = r时，具有至少公式（III）的加速的互连网络以严格的非阻塞和确定性方式根据本发明通过在每个切换时间内调度最多r个分组来切换至多r个切换时间。而在互联网络中，至少加速公式（IV），系统可以在后面可以非阻塞和确定性的方式运行。该系统还提供从输入端口到输出端口的数据包的端到端保证带宽和延迟。在所有实施例中，互连网络可以是交叉网络，共享存储器网络，闭路网络，超立方体网络或任何内部非阻塞互连网络或网络网络。

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