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1. 发明申请

WO1997014289A2 PROTOCOL FOR COMMUNICATION WITH DYNAMIC MEMORY 审中-公开
标题翻译：与动态记忆通信协议
公开(公告)号：WO1997014289A2
公开(公告)日：1997-04-24
申请号：PCT/US1996016835
申请日：1996-10-18
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , BARTH, Richard, Maurice , WARE, Frederick, Abbot , DILLON, John, Bradly , STARK, Donald, Charles , HAMPEL, Craig, Edward , GRIFFIN, Matthew, Murdy
IPC分类号： G06F12/00 , G06F13/16 , G11C5/06 , G11C7/10 , G11C7/22 , G11C8/12 , G11C11/401
CPC分类号： G11C7/22 , G06F13/161 , G11C5/066 , G11C7/10 , G11C7/1072 , G11C8/12
摘要： A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.
摘要翻译：提供了一种用于在计算机系统内执行数据传输的系统和方法。该系统包括控制器，该控制器被配置为动态地调整执行一系列数据传送操作所需的通信的交错，以最大限度地利用要在其上执行通信的信道的利用。控制器能够通过用与控制信息分开发送的选通信号通过信令数据传送的开始来改变请求数据传送的控制信息的传输与数据传送的执行之间的时间间隔。控制器能够通过启动具有终止信号的数据传送的终止来推迟在操作中传送多少数据的确定。该方法提供了用于区分同一行上承载的相同控制信号的技术。该系统包括具有控制电路的存储器件，其允许不超过一个由任何给定电源线供电的存储体执行感测或预充电操作。

2. 发明申请

WO1997003445A1 BLOCK WRITE FOR MEMORY COMPONENTS 审中-公开
标题翻译：内存组件的块写
公开(公告)号：WO1997003445A1
公开(公告)日：1997-01-30
申请号：PCT/US1996011436
申请日：1996-07-08
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , WARE, Frederick, Abbott , BARTH, Richard, Maurice , HAMPEL, Craig , DILLON, John, Bradly , GARRETT, Billy, W.
IPC分类号： G11C07/00
CPC分类号： G11C7/1015
摘要： Circuitry for performing a memory block write is described. The memory block includes b block words, each block word having t block bytes. Each block byte has s bits of memory. Each block byte is associated with at least two associated mask value bits. A constant register has at least s x t bits of memory arranged as t constant bytes, each constant byte storing a constant value, each constant byte associated with one block of every block word. The block write circuitry includes control circuitry for selecting one of a normal write function and a block write function in accordance with a block write signal. When the block write function is selected, the control circuitry stores the associated constant value in every nonmasked block byte substantially simultaneously in accordance with a value of the associated mask value bits.
摘要翻译：描述用于执行存储器块写入的电路。存储块包括b个块字，每个块字具有t个块字节。每个块字节都有s位存储器。每个块字节与至少两个关联的掩码值位相关联。一个常数寄存器至少有一个s x t位的存储器被排列成t个恒定字节，每个恒定字节存储一个恒定值，每个恒定字节与每个块字的一个块相关联。块写入电路包括用于根据块写入信号选择正常写入功能和块写入功能之一的控制电路。当选择块写入功能时，控制电路根据相关联的掩码值位的值基本上同时地存储每个非屏蔽块字节中的关联常数值。

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