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1. 发明申请

WO2023028399A1 METHODS AND APPARATUS FOR A NOVEL MEMORY ARRAY 审中-公开
公开(公告)号：WO2023028399A1
公开(公告)日：2023-03-02
申请号：PCT/US2022/073810
申请日：2022-07-15
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： G11C16/12 , G11C16/24
摘要： Methods and apparatus for a novel memory array are disclosed. In an embodiment, a method is provided for reading a dynamic random-access memory (DRAM) array. The method includes activating the bit line select gates to equalize voltage levels on a plurality of bit lines, deactivating the bit line select gates to maintain the equalized voltage levels on the plurality of bit lines using a bit line capacitance associated with each bit line, and activating a selected word line to access selected memory cells connected to the selected word line. The method also includes activating bit line select gates to pass first data from a first bit line and second data from a second bit line to the sense amplifier. The first data is from a selected memory cell and the second data is reference data. The method also includes determining sensed data from the first and second data.

2. 发明申请

WO2016164318A1 TWO TRANSISTOR SONOS FLASH MEMORY 审中-公开
标题翻译：两个晶体管SONOS闪存
公开(公告)号：WO2016164318A1
公开(公告)日：2016-10-13
申请号：PCT/US2016/025916
申请日：2016-04-04
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： G11C16/0433 , G11C16/0466 , G11C16/06 , G11C16/10 , H01L27/1157
摘要： A two transistor SONOS flash memory is disclosed. In one aspect, an apparatus, includes a control gate transistor having source and drain diffusions deposited in an N-well, a charge-trapping region formed on the N-well that overlaps the source and drain diffusions, and a control gate formed on the charge-trapping region. A channel region of the N-well between the source and drain diffusions is less than 90nm in length. The apparatus also includes a select gate transistor having a select source diffusion deposited in the N-well. A drain side of the select gate transistor shares the source diffusion. A channel region of the N-well between the select source diffusion and the source diffusion also is less than 90nm in length.
摘要翻译：公开了一种双晶体管SONOS闪速存储器。一方面，一种装置包括：控制栅极晶体管，其具有沉积在N阱中的源极和漏极扩散层;形成在与所述源极和漏极扩散器重叠的所述N阱上的电荷俘获区域;以及控制栅极，电荷捕获区域。源极和漏极扩散之间的N阱的沟道区域的长度小于90nm。该装置还包括具有沉积在N阱中的选择源扩散的选择栅极晶体管。选择栅极晶体管的漏极侧共享源极扩散。选择源扩散和源极扩散之间的N阱的沟道区域的长度小于90nm。

3. 发明申请

WO2016037146A1 METHOD AND APPARATUS FOR WRITING NONVOLATILE MEMORY USING MULTIPLE-PAGE PROGRAMMING 审中-公开
标题翻译：使用多页编程编写非易失性存储器的方法和装置
公开(公告)号：WO2016037146A1
公开(公告)日：2016-03-10
申请号：PCT/US2015/048718
申请日：2015-09-04
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： G06F12/06
CPC分类号： G11C16/10 , G11C7/1039 , G11C16/08 , G11C16/16 , G11C16/32
摘要： A method of storing information or data in a nonvolatile memory device with multiple-page programming is disclosed. The method, in one aspect, is able to activate a first drain select gate ("DSG") signal. After loading the first data from a bit line ("BL") to a nonvolatile memory page of a first memory block in response to activation of the first DSG signal during a first clock cycle, the first DSG signal is deactivated. Upon activating a second DSG signal, the second data is loaded from the BL to a nonvolatile memory page of a second memory block. The first data and the second data are simultaneously written to the first memory block and the second memory block, respectively.
摘要翻译：公开了一种在具有多页编程的非易失性存储装置中存储信息或数据的方法。该方法在一个方面能够激活第一漏极选择栅极（“DSG”）信号。响应于在第一时钟周期期间第一DSG信号的激活将第一数据从位线（“BL”）加载到第一存储器块的非易失性存储器页面之后，第一DSG信号被去激活。在激活第二DSG信号时，将第二数据从BL加载到第二存储器块的非易失性存储器页。第一数据和第二数据分别同时写入第一存储器块和第二存储器块。

4. 发明申请

WO2021011582A1 METHODS AND APPARATUS FOR READING NAND FLASH MEMORY 审中-公开
公开(公告)号：WO2021011582A1
公开(公告)日：2021-01-21
申请号：PCT/US2020/042019
申请日：2020-07-14
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： G11C16/24 , G11C16/26
摘要： Methods and apparatus for reading NAND flash memory are disclosed. In an embodiment, a method is provided for reading a NAND flash memory that includes strings of memory cells that are coupled to bit lines and word lines. The method includes precharging a plurality of bit lines to a precharge voltage level, and applying a sequence of word line voltages to a selected word line. The method also includes initiating discharge of one or more bit lines associated with one or more cells, respectively. The method also includes controlling discharging current of discharging bit lines to achieve identical discharge rates, waiting for a discharging time period for each bit line that is discharging, and latching bit line data at an end of each discharge time period.

5. 发明申请

WO2020097098A3 METHODS AND APPARATUS FOR A THREE-DIMENSIONAL (3D) ARRAY HAVING ALIGNED DEEP-TRENCH CONTACTS 审中-公开
公开(公告)号：WO2020097098A3
公开(公告)日：2020-05-14
申请号：PCT/US2019/059892
申请日：2019-11-05
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： H01L43/08 , H01L43/12 , G11C11/16
摘要： Methods and apparatus for a three-dimensional (3D) array having aligned deep-trench contacts are disclosed. In an embodiment, a method includes forming an array stack having conductor layers and insulator layers, and forming a hard mask on top of the array stack. The hard mask includes a plurality of holes. The method also includes forming a pull-back mask on top of the hard mask, and etching the pull-back mask so that at least one hole of the hard mask is exposed. The method also includes etching through one or more exposed holes of the hard mask to remove one or more layers of the array stack.

6. 发明申请

WO2016154597A1 THREE-DIMENSIONAL DOUBLE DENSITY NAND FLASH MEMORY 审中-公开
标题翻译：三维双密度NAND闪存
公开(公告)号：WO2016154597A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/024358
申请日：2016-03-25
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： H01L29/792 , H01L23/525 , H01L27/115 , H01L29/51 , G11C11/56 , G11C16/00
CPC分类号： H01L27/11582 , G11C11/5621 , G11C16/0475 , G11C16/0483 , H01L23/525 , H01L27/11565 , H01L27/1157
摘要： A three-dimensional double-density NAND flash memory device is disclosed. In one aspect, an apparatus includes a three dimensional stacked configuration of word line layers separated by insulating layers. The stacked configuration includes a selected number of the word line layers. The apparatus also includes an array of NAND strings deposited within the stacked configuration and perpendicular to a top surface of the stacked configuration. Each NAND string includes a charge-trapping layer that extends through the selected number of word line layers. The apparatus also includes one or more slits through the stacked configuration that divide each word line layer into a plurality of word line regions. The charge-trapping layer of each NAND string is coupled to two word line regions in each word line layer to form two charge-trapping regions to store two data bits in each word line layer.
摘要翻译：公开了一种三维双密度NAND闪速存储器件。一方面，一种装置包括由绝缘层隔开的字线层的三维堆叠结构。堆叠配置包括所选数量的字线层。该装置还包括沉积在堆叠构造中并垂直于堆叠构造的顶表面的NAND串的阵列。每个NAND串包括延伸穿过选定数量的字线层的电荷捕获层。该装置还包括通过将每个字线层划分成多个字线区域的堆叠构造的一个或多个狭缝。每个NAND串的电荷捕获层耦合到每个字线层中的两个字线区域，以形成两个电荷捕获区域，以在每个字线层中存储两个数据位。

7. 发明申请

WO2022072906A1 METHODS AND APPARATUS FOR NAND FLASH MEMORY 审中-公开
公开(公告)号：WO2022072906A1
公开(公告)日：2022-04-07
申请号：PCT/US2021/053268
申请日：2021-10-01
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： G06F12/00
摘要： Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level cells in a memory array. The memory array includes a plurality of planes and each plane includes a plurality of bit lines. The method includes storing multiple data bits in a first group of planes, one data bit per plane. The multiple data bits are stored in bit line capacitances of the first group of planes. The method also includes programming a selected multiple-level cell in a selected plane according to the multiple data bits that are stored in the bit line capacitances of the first group of planes. The selected plane is not one of the first group of planes.

8. 发明申请

WO2020102815A1 METHODS AND APPARATUS FOR NAND FLASH MEMORY 审中-公开
公开(公告)号：WO2020102815A1
公开(公告)日：2020-05-22
申请号：PCT/US2019/062057
申请日：2019-11-18
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10
摘要： Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a NAND flash memory includes setting programming conditions on word lines to set up programming of multiple memory cells associated with multiple bit lines, and sequentially enabling bit line select gates to load data from a page buffer to the multiple bit lines of the memory. After each bit line is loaded with selected data, an associated bit line select gate is disabled so that the selected data is maintained on the bit line using bit line capacitance. The method also includes waiting for a programming interval to complete after all the bit lines are loaded with data to program the multiple memory cells associated with the multiple bit lines. At least a portion of the multiple memory cells are programmed simultaneously.

9. 发明申请

WO2016172636A1 Dual Function Hybrid Memory Cell 审中-公开
标题翻译：双功能混合存储单元
公开(公告)号：WO2016172636A1
公开(公告)日：2016-10-27
申请号：PCT/US2016/029059
申请日：2016-04-22
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： H01L29/792 , H01L21/28 , G11C11/56 , G11C16/02
CPC分类号： G11C16/0475 , G11C7/1015 , G11C11/401 , G11C16/0466 , G11C16/10 , G11C2211/4016 , H01L21/28282 , H01L27/1211 , H01L29/4234 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A dual function hybrid memory cell is disclosed. In one aspect, the memory cell includes a substrate, a bottom charge-trapping region formed on the substrate, a top charge-trapping region formed on the bottom charge-trapping region, and a gate layer formed on the top charge trapping region. In another aspect, a method for programming a memory cell having a substrate, a bottom charge-trapping layer, a top charge-trapping layer, and a gate layer is disclosed. The method includes biasing a channel region of the substrate, applying a first voltage differential between the gate layer and the channel region, injecting charge into the bottom charge-trapping layer from the channel region based on the first voltage differential. The method also includes applying a second voltage differential between the gate layer and the channel region and injecting charge from the bottom charge-trapping layer into the top charge-trapping layer based on the second voltage differential.
摘要翻译：公开了一种双功能混合存储器单元。一方面，存储单元包括基板，形成在基板上的底部电荷俘获区域，形成在底部电荷俘获区域上的顶部电荷俘获区域和形成在顶部电荷俘获区域上的栅极层。另一方面，公开了一种用于编程具有衬底，底部电荷俘获层，顶部电荷俘获层和栅极层的存储器单元的方法。该方法包括偏置衬底的沟道区域，在栅极层和沟道区域之间施加第一电压差，基于第一电压差将电荷从沟道区域注入底部电荷俘获层。该方法还包括在栅极层和沟道区域之间施加第二电压差，并且基于第二电压差将电荷从底部电荷俘获层注入顶部电荷俘获层。

10. 发明申请

WO2016049375A1 METHOD AND APPARATUS FOR STORING INFORMATION USING A MEMORY ABLE TO PERFORM BOTH NVM AND DRAM FUNCTIONS 审中-公开
标题翻译：使用存储器来存储信息以实现两个NVM和DRAM功能的方法和装置
公开(公告)号：WO2016049375A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/052056
申请日：2015-09-24
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： G11C7/10
CPC分类号： G11C14/0009
摘要： A memory device is able to store data using both on-chip dynamic random-access memory ("DRAM") and nonvolatile memory ("NVM"). The memory device, in one aspect, includes NVM cells, word lines ("WLs"), a cell channel, and a DRAM mode select. The NVM cells are capable of retaining information persistently and the WLs are configured to select one of the NVM cells to be accessed. The cell channel, in one embodiment, is configured to interconnect the NVM cells to form a NVM string. The DRAM mode select can temporarily store data in the cell channel when the DRAM mode select is active.
摘要翻译：存储器件能够使用片上动态随机存取存储器（“DRAM”）和非易失性存储器（“NVM”）来存储数据。在一个方面，存储器件包括NVM单元，字线（“WL”），单元通道和DRAM模式选择。 NVM单元能够持续保留信息，WL被配置为选择要访问的NVM单元之一。在一个实施例中，小区信道被配置为互连NVM小区以形成NVM串。当DRAM模式选择被激活时，DRAM模式选择可临时存储单元通道中的数据。

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