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1. 发明申请

WO2010049218A1 A HIGH RADIX DIGITAL MULTIPLIER 审中-公开
标题翻译：高分辨率数字多路复用器
公开(公告)号：WO2010049218A1
公开(公告)日：2010-05-06
申请号：PCT/EP2009/062295
申请日：2009-09-23
申请人： AUDIOASICS A/S , MORTENSEN, Mikael
发明人： MORTENSEN, Mikael
IPC分类号： G06F7/48 , G06F7/533
CPC分类号： G06F7/5336 , G06F7/4824
摘要： The present invention relates to power and hardware efficient digital multipliers configured to multiply an N-bit multiplicand with an M-bit multiplier. The digital multipliers comprise efficient partial product generation through sharing of at least one partial product result.
摘要翻译：本发明涉及被配置为将N位被乘数与M位乘法器相乘的功率和硬件有效数字乘法器。数字乘法器通过共享至少一个部分乘积结果来构成有效的部分乘积生成。

2. 发明申请

WO2004070609A1 論理演算回路、論理演算装置および論理演算方法审中-公开
标题翻译：逻辑计算电路，逻辑计算装置和逻辑计算方法
公开(公告)号：WO2004070609A1
公开(公告)日：2004-08-19
申请号：PCT/JP2004/001021
申请日：2004-02-02
申请人：ローム株式会社 , 亀山充隆 , 羽生貴弘 , 木村啓明 , 藤森敬和 , 中村孝 , 高須秀視
发明人：亀山充隆 , 羽生貴弘 , 木村啓明 , 藤森敬和 , 中村孝 , 高須秀視
IPC分类号： G06F7/00
CPC分类号： G11C15/046 , G06F7/4824 , G06F7/5332 , G06F2207/3884
摘要：不揮発性記憶素子を用いて、データの記憶、および、高信頼性かつ高速なデータの論理演算が可能な論理演算回路等を提供する。負荷用の強誘電体コンデンサＣs'の残留分極状態ｓ'が記憶用の強誘電体コンデンサＣsの残留分極状態ｓと反対になるよう、強誘電体コンデンサＣs'の残留分極状態を積極的に変更する。演算動作において基準電位ｃ＝０とした場合、残留分極状態ｓ（第１の被演算データ）＝０の強誘電体コンデンサＣsに第２の被演算データｘ＝１を付与しても強誘電体コンデンサＣsは分極反転を起こさない。ｓ＝０、ｘ＝１以外の組み合わせでも強誘電体コンデンサＣsは分極反転を起こさない。また、ｓ＝０の強誘電体コンデンサＣsにｘ＝１を付与したとき結合ノードが示す電位ＶA＝ＶA(0)と、ｓ＝１の強誘電体コンデンサＣsにｘ＝１を付与したとき結合ノードが示す電位ＶA＝ＶA(1)との差が大きい。
摘要翻译：提供了一种能够通过使用非易失性存储元件进行数据存储和高可靠性和高速数据逻辑计算的逻辑计算电路。积极地修改铁电电容器Cs'的残留极化状态，使得用于负载的铁电电容器Cs'的残留极化状态s'与用于存储的强电介质电容器Cs的残留极化状态s相反。当计算动作中的基准电位c = 0时，即使将第二计算数据x = 1添加到剩余极化状态s（第一计算数据）= 0的强电介质电容器Cs，铁电电容器Cs也不产生极化反转。铁素体电容器Cs即使在组合s = 0和x = 1之外也不引起极化反转。此外，当施加x = 1时，由耦合节点表示的电位VA = VA（0）之间存在较大的差异到s = 1的铁电电容器Cs和x = 1时由耦合节点表示的电位VA = VA（1）施加到s = 1的铁电电容器Cs。

3. 发明申请

WO9322720A3 PROCESS FOR FINDING THE RECIPROCAL OF A DIVISOR BY STEPWISE APPROXIMATION 审中-公开
标题翻译：通过逐步逼近发现一个分支机构的过程
公开(公告)号：WO9322720A3
公开(公告)日：1994-03-31
申请号：PCT/AT9300074
申请日：1993-04-29
申请人： JOHANN KAMLEITHNER FA
发明人： VACARIU CORNELL
IPC分类号： G06F7/48 , G06F7/52 , H03M7/06 , G06F7/49
CPC分类号： G06F7/5332 , G06F7/4824 , G06F7/535 , G06F7/5375 , H03M7/06
摘要： A novel process and a pure hardware and architecturally symmetrical division circuit is described which recursively and bidirectionally finds a quotient from a dividend and a divisor by approximation. It is thus possible to start the calculation with the highest or lowest position value or at the same time with the two extremes of the divisor/divident/quotient, in a parallel process. The division circuit therefore consists of four parts, with two symmetrical pairs. The left-hand main circuit (1), which is symmetrical with the right-hand sub-circuit (3), processes the divisor and, via the two control signals D/I and AS, controls the left hand sub-circuit (2) which is symmetrical with the right-hand sub-circuit (4) and processes the dividend in order to find the quotient. The two symmetrical parts can operate mutually independently, i.e. separately, thus making it possible to perform two different division operations at the same time via the two symmetrical halves. The division process can thus be performed bidirectionally or on one side (left or right). The operands may be represented in a non-redundant format or in a digit format with a sign, where 'carry-ripple' transfer can be prevented by the representation strategy of the 'non-neighbouring non-zero trits' and a region centred on '1' will be alocated to the absolute value of the mantissa (M) after the standardisation process.

4. 发明申请

WO01046795A2 METHOD AND APPARATUS FOR PERFORMING SINGLE-CYCLE ADDITION OR SUBTRACTION AND COMPARISON IN REDUNDANT FORM ARITHMETIC 审中-公开
标题翻译：用于执行单周期添加或减少的冗余方法和比较方法
公开(公告)号：WO01046795A2
公开(公告)日：2001-06-28
申请号：PCT/US2000/042165
申请日：2000-11-13
IPC分类号： G06F7/02 , G06F7/48 , G06F7/50 , G06F7/509 , G06F7/38
CPC分类号： G06F7/5095 , G06F7/02 , G06F7/4824
摘要： A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic oepration is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.
摘要翻译：公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，还可以减去以冗余形式接收的数字，包括从旁路电路接收的数字。然后使用非传播比较器电路将给定值与运算电路的结果进行比较，以确定结果是否等于给定值。可以在整个电路中不传播进位信号来实现上述所有操作。该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。它还包括向算术电路提供调整输入以增加通过运算电路产生的结果。如果算术运算是减法运算，则该调整将使运算电路产生冗余形式的有效结果作为减法运算的结果。然后将结果与使用非传播比较器的给定值进行比较，以确定结果与给定值的相等或不等式。

5. 发明申请

WO00005837A1 TIMING ATTACK RESISTANT CRYPTOGRAPHIC SYSTEM 审中-公开
标题翻译：时序攻击耐克系统
公开(公告)号：WO00005837A1
公开(公告)日：2000-02-03
申请号：PCT/CA1999/000658
申请日：1999-07-21
IPC分类号： G09C1/00 , G06F7/48 , G06F7/72 , H04L9/30
CPC分类号： G06F9/30058 , G06F7/4824 , G06F7/725 , G06F2207/7261 , H04L9/005 , H04L9/3066
摘要： A method for determining a result of a group operation performed an integral number of times on a selected element of the group, the method comprises the steps of: representing the integral number as a binary vector; initializing an intermediate element to the group identity element; selecting successive bits, beginning with a left most bit, of the vector. For each of the selected bits; performing the group operation on the intermediate element to derive a new intermediate element; replacing the intermediate element with the new intermediate element; performing the group operation on the intermediate element and an element, selected from the group consisting of: the group element if the selected bit is a one; and an inverse element of the group element if the selected bit is a zero; replacing the intermediate element with the new intermediate element. In a final step, performing the group operation on the intermediate value and the inverse element if the last selected bit is a zero; and replacing the intermediate element therewith, to obtain the result, whereby each of the bits of the integral is processed with substantially equal operations thereby minimizing timing attacks on the cryptographic system.
摘要翻译：一种用于确定组操作的结果对组的所选元素执行整数次的方法，所述方法包括以下步骤：将所述积分数表示为二进制向量; 将中间元素初始化为组标识元素; 选择向量开始的最左位的连续位。对于每个选定的位; 对中间元素执行组操作以导出新的中间元素; 用新的中间元件代替中间元件; 对中间元素执行组操作，以及从由以下组成的组中选择的元素：组元素，如果所选择的位是一个; 如果所选择的位为零，则组元素的反向元素; 用新的中间元件代替中间元件。在最后一步中，对中间值执行组操作，如果最后一个选择的位为零，则执行逆元素; 并且用其替换中间元件，以获得结果，由此以大致相等的操作处理积分的每个比特，从而最小化对密码系统的定时攻击。

6. 发明申请

WO1993022720A2 PROCESS FOR FINDING THE RECIPROCAL OF A DIVISOR BY STEPWISE APPROXIMATION 审中-公开
标题翻译：制造方法循序渐进的方式BY除数的扫掠价值
公开(公告)号：WO1993022720A2
公开(公告)日：1993-11-11
申请号：PCT/AT1993000074
申请日：1993-04-29
申请人： FIRMA JOHANN KAMLEITHNER , VACARIU, Cornell
发明人： FIRMA JOHANN KAMLEITHNER
IPC分类号： G06F07/52
CPC分类号： G06F7/5332 , G06F7/4824 , G06F7/535 , G06F7/5375 , H03M7/06
摘要： A novel process and a pure hardware and architecturally symmetrical division circuit is described which recursively and bidirectionally finds a quotient from a dividend and a divisor by approximation. It is thus possible to start the calculation with the highest or lowest position value or at the same time with the two extremes of the divisor/divident/quotient, in a parallel process. The division circuit therefore consists of four parts, with two symmetrical pairs. The left-hand main circuit (1), which is symmetrical with the right-hand sub-circuit (3), processes the divisor and, via the two control signals D/I and AS, controls the left hand sub-circuit (2) which is symmetrical with the right-hand sub-circuit (4) and processes the dividend in order to find the quotient. The two symmetrical parts can operate mutually independently, i.e. separately, thus making it possible to perform two different division operations at the same time via the two symmetrical halves. The division process can thus be performed bidirectionally or on one side (left or right). The operands may be represented in a non-redundant format or in a digit format with a sign, where "carry-ripple" transfer can be prevented by the representation strategy of the "non-neighbouring non-zero trits" and a region centred on "1" will be alocated to the absolute value of the mantissa (M) after the standardisation process.

7. 发明申请

WO2004092946A1 DIGITAL ENGINEERING METHOD AND PROCESSOR OF THE MIXED Q N-ARY AND CARRY LINE 审中-公开
公开(公告)号：WO2004092946A1
公开(公告)日：2004-10-28
申请号：PCT/CN2004/000375
申请日：2004-04-19
IPC分类号： G06F7/00
CPC分类号： G06F7/4824
摘要： The present invention relates to the field of digital engineering method and processor, it provides a new digital engineering method, improves operational speed. The mixed Q N-ary and carry line of digital engineering method according to the present invention includes: A digital sign is added to every bit of the common Q N-ary digitals participating in the operation , there are k mixed N-ary digitals to participate in the operation. Sums up k mixed Q N-ary at the same time. Adding by bit beginning with the lowest bit, i. e., at a certain bit, two digitals of the above described k digitals are taken and added to generate "addition by bit", and the sum is taken into the next operation layer as "partial sum", meanwhile the acquired "mixed digital carry" is put into the high-order bit which is close to the bit that is any carry line of the next operation layer. The operations don't stop until it generates "mixed Q N-ary carry" line. Then the sum obtained by the last "addition by bit" is the result if addition operation. The present provides a processor with mixed Q N-ary and carry line operation.

8. 发明申请

WO2003009473A1 PROCESSING OF QUINARY DATA 审中-公开
标题翻译：加工数据
公开(公告)号：WO2003009473A1
公开(公告)日：2003-01-30
申请号：PCT/IE2002/000106
申请日：2002-07-17
申请人： MASSANA RESEARCH LIMITED , MCELROY, Ciaran , CURRAN, Philip , MOLINA NAVARRO, Alberto
发明人： MCELROY, Ciaran , CURRAN, Philip , MOLINA NAVARRO, Alberto
IPC分类号： H03H17/06
CPC分类号： H03H17/06 , G06F7/4824 , H03H17/0233
摘要： A FIR in a Gigabit transceiver represents data words in three bits: SIGN representing word sign, SHIFT representing requirement for a shift operation, and ZERO indicating whether the word is zero. An AND gate ANDs a multiplier and the ZERO bit, an XOR gate XORs the SIGN bit and the output of the AND gate, and a multiplier left-shifts the coefficient using the SHIFT bit and the output of the XOR gate. The circuit has a very low gate count.
摘要翻译：千兆收发器中的FIR表示三位数据字：SIGN表示字符号，SHIFT表示移位操作的要求，ZERO表示字是否为零。与门AND乘法器和零位，异或门将SIGN位和与门的输出异或，乘法器使用SHIFT位和XOR门的输出来左移系数。电路具有非常低的门数。

9. 发明申请

WO0146795A3 METHOD AND APPARATUS FOR PERFORMING SINGLE-CYCLE ADDITION OR SUBTRACTION AND COMPARISON IN REDUNDANT FORM ARITHMETIC 审中-公开
标题翻译：用于执行单周期添加或减少的冗余方法和比较方法
公开(公告)号：WO0146795A3
公开(公告)日：2002-01-03
申请号：PCT/US0042165
申请日：2000-11-13
申请人： INTEL CORP , GROCHOWSKI ED , SHARMA VINOD , BHUSHAN BHARAT , CRAWFORD JOHN
发明人： GROCHOWSKI ED , SHARMA VINOD , BHUSHAN BHARAT , CRAWFORD JOHN
IPC分类号： G06F7/02 , G06F7/48 , G06F7/50 , G06F7/509 , G06F7/49
CPC分类号： G06F7/5095 , G06F7/02 , G06F7/4824
摘要： A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic oepration is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.
摘要翻译：公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，还可以减去以冗余形式接收的数字，包括从旁路电路接收的数字。然后使用非传播比较器电路将给定值与运算电路的结果进行比较，以确定结果是否等于给定值。可以在整个电路中不传播进位信号来实现上述所有操作。该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。它还包括向算术电路提供调整输入以增加通过运算电路产生的结果。如果算术运算是减法运算，则该调整将使运算电路产生冗余形式的有效结果作为减法运算的结果。然后将结果与使用非传播比较器的给定值进行比较，以确定结果与给定值的相等或不等式。

10. 发明申请

WO99031573A1 SEMICONDUCTOR CIRCUIT FOR ARITHMETIC OPERATION AND METHOD OF ARITHMETIC OPERATION 审中-公开
标题翻译：用于算术运算的半导体电路和算术运算方法
公开(公告)号：WO99031573A1
公开(公告)日：1999-06-24
申请号：PCT/JP1998/005720
申请日：1998-12-17
IPC分类号： G06F7/00 , G06F7/48 , G06F7/50 , G06F7/506
CPC分类号： G06F7/4824 , G06F7/506
摘要： A semiconductor circuit for arithmetic operation, which uses a reduced circuit area and provides high-speed processing by restricting nonessentials. The semiconductor circuit comprises an arithmetic circuit (adders 1-3) and delay means (memory 4). The arithmetic circuit includes arithmetic units for operation on input data, and they operate on digits of input data in a period of operation time, and produce results of operation, together with data corresponding to a carry, if any. The output from the arithmetic circuit is delayed by one period of operation time through the delay means.
摘要翻译：一种用于算术运算的半导体电路，其使用简化的电路区域并通过限制不必要的方式提供高速处理。半导体电路包括运算电路（加法器1-3）和延迟装置（存储器4）。算术电路包括用于对输入数据进行操作的算术单元，并且它们在操作时间段内对输入数据的数字进行操作，并产生与进位相对应的数据（如果有的话）的操作结果。算术电路的输出通过延迟装置延迟一个操作时间周期。

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