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1. 发明申请

WO2006074024A3 A MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY OF INSTRUCTION SEQUENCERS 审中-公开
标题翻译：基于指令序列的多个指令执行机制
公开(公告)号：WO2006074024A3
公开(公告)日：2006-10-26
申请号：PCT/US2005047328
申请日：2005-12-28
申请人： INTEL CORP , WANG HONG , SHEN JOHN , GROCHOWSKI ED , HELD JAMES PAUL , BIGBEE BRYANT , KAUSHIK SHIVNANDAN D , CHINYA GAUTHAM , ZOU XIANG , HAMMARLUND PER , TIEN XINMIN , AGGARWAL ANIL , RODGERS SCOTT DION , PATEL BAIJU V , HANKINS RICHARD
发明人： WANG HONG , SHEN JOHN , GROCHOWSKI ED , HELD JAMES PAUL , BIGBEE BRYANT , KAUSHIK SHIVNANDAN D , CHINYA GAUTHAM , ZOU XIANG , HAMMARLUND PER , TIEN XINMIN , AGGARWAL ANIL , RODGERS SCOTT DION , PATEL BAIJU V , HANKINS RICHARD
IPC分类号： G06F9/48
CPC分类号： G06F9/3851 , G06F9/4843
摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
摘要翻译：在一个实施例中，提供了一种方法。该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。

2. 发明申请

WO0146795A3 METHOD AND APPARATUS FOR PERFORMING SINGLE-CYCLE ADDITION OR SUBTRACTION AND COMPARISON IN REDUNDANT FORM ARITHMETIC 审中-公开
标题翻译：用于执行单周期添加或减少的冗余方法和比较方法
公开(公告)号：WO0146795A3
公开(公告)日：2002-01-03
申请号：PCT/US0042165
申请日：2000-11-13
申请人： INTEL CORP , GROCHOWSKI ED , SHARMA VINOD , BHUSHAN BHARAT , CRAWFORD JOHN
发明人： GROCHOWSKI ED , SHARMA VINOD , BHUSHAN BHARAT , CRAWFORD JOHN
IPC分类号： G06F7/02 , G06F7/48 , G06F7/50 , G06F7/509 , G06F7/49
CPC分类号： G06F7/5095 , G06F7/02 , G06F7/4824
摘要： A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic oepration is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.
摘要翻译：公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，还可以减去以冗余形式接收的数字，包括从旁路电路接收的数字。然后使用非传播比较器电路将给定值与运算电路的结果进行比较，以确定结果是否等于给定值。可以在整个电路中不传播进位信号来实现上述所有操作。该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。它还包括向算术电路提供调整输入以增加通过运算电路产生的结果。如果算术运算是减法运算，则该调整将使运算电路产生冗余形式的有效结果作为减法运算的结果。然后将结果与使用非传播比较器的给定值进行比较，以确定结果与给定值的相等或不等式。

3. 发明申请

WO2006074024A2 A MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY OF INSTRUCTION SEQUENCERS 审中-公开
标题翻译：基于指令集的一种机制基于多个指令序列的线程执行
公开(公告)号：WO2006074024A2
公开(公告)日：2006-07-13
申请号：PCT/US2005/047328
申请日：2005-12-28
申请人： INTEL CORPORATION , WANG, Hong , SHEN, John , GROCHOWSKI, Ed , HELD, James, Paul , BIGBEE, Bryant , KAUSHIK, Shivnandan, D. , CHINYA, Gautham , ZOU, Xiang , HAMMARLUND, Per , TIEN, Xinmin , AGGARWAL, Anil , RODGERS, Scott, Dion , PATEL, Baiju, V. , HANKINS, Richard
发明人： WANG, Hong , SHEN, John , GROCHOWSKI, Ed , HELD, James, Paul , BIGBEE, Bryant , KAUSHIK, Shivnandan, D. , CHINYA, Gautham , ZOU, Xiang , HAMMARLUND, Per , TIEN, Xinmin , AGGARWAL, Anil , RODGERS, Scott, Dion , PATEL, Baiju, V. , HANKINS, Richard
IPC分类号： G06F9/48
CPC分类号： G06F9/3851 , G06F9/4843
摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
摘要翻译：在一个实施例中，提供了一种方法。该方法包括响应于在应用级程序控制下的第二指令定序器上执行用户级指令而管理第一指令定序器上的用户级线程。第一个用户级线程在第二个指令序列器上运行，并包含一个或多个用户级指令。第一个用户级指令至少有1）一个引用一个或多个指令定序器的字段，或者2）当代码执行时，隐含地引用一个指向特定地寻址一个或多个指令定序器的代码的指针。

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