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1. 发明申请

WO2008116154A1 SMART ACCUMULATOR FOR FINITE-PRECISION ARITHMETIC 审中-公开
标题翻译：智能累加器用于精确计算
公开(公告)号：WO2008116154A1
公开(公告)日：2008-09-25
申请号：PCT/US2008/057825
申请日：2008-03-21
申请人： QUALCOMM INCORPORATED , TSAI, Ming-Chang , SRINIVAS, Pillappakkam , SENIOR, Ric
发明人： TSAI, Ming-Chang , SRINIVAS, Pillappakkam , SENIOR, Ric
IPC分类号： G06F7/509
CPC分类号： G06F7/509
摘要： Systems, methods, and devices that facilitate finite-precision data accumulation by utilizing precision binning and queuing are provided. A precision range of a data element received into a queue can be determined. Further, a stored data element of like precision can be selected. The stored data element can be added with the data element received into the queue to generate a resultant data element. The resultant data element can be stored in a memory location or the queue as a function of like precision range.
摘要翻译：提供了通过利用精确分箱和排队来促进有限精度数据累积的系统，方法和设备。可以确定接收到队列中的数据元素的精确范围。此外，可以选择存储的类似精度的数据元素。存储的数据元素可以与接收到队列中的数据元素相加以生成结果数据元素。结果数据元素可以作为类似精度范围的函数存储在存储器位置或队列中。

2. 发明申请

WO2008022331A3 MULTI-STAGE FLOATING-POINT ACCUMULATOR 审中-公开
公开(公告)号：WO2008022331A3
公开(公告)日：2008-02-21
申请号：PCT/US2007/076242
申请日：2007-08-17
申请人： QUALCOMM INCORPORATED , DU, Yun , YU, Chun , JIAO, Guofang
发明人： DU, Yun , YU, Chun , JIAO, Guofang
IPC分类号： G06F7/485 , G06F7/509 , G06F5/01
摘要： A multi-stage floating-point accumulator includes at least two stages and is capable of operating at higher speed. In one design, the floating-point accumulator includes first and second stages. The first stage includes three operand alignment units, two multiplexers, and three latches. The three operand alignment units operate on a current floating-point value, a prior floating-point value, and a prior accumulated value. A first multiplexer provides zero or the prior floating-point value to the second operand alignment unit. A second multiplexer provides zero or the prior accumulated value to the third operand alignment unit. The three latches couple to the three operand alignment units. The second stage includes a 3-operand adder to sum the operands generated by the three operand alignment units, a latch, and a post alignment unit.

3. 发明申请

WO2006059267A3 ELECTRONIC DEVICE HAVING MULTI OPERAND ARITHMETIC CIRCUITRY 审中-公开
公开(公告)号：WO2006059267A3
公开(公告)日：2006-06-08
申请号：PCT/IB2005/053929
申请日：2005-11-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SAWITZKI, Sergei
发明人： SAWITZKI, Sergei
IPC分类号： G06F7/509 , G06F7/499
摘要： An electronic device comprising an arithmetic circuitry (AC) for performing at least one of an addition or a subtraction of more than two binary input numbers (BINl - BIN4) is provided, wherein at least two of the binary input numbers differ in their bit-widths. The arithmetic circuitry (AC) comprises an extension means (EUl - EU3) for performing a sign and/or a zero extension of at least one of the binary input numbers (BINl - BIN4). Further, the arithmetic circuitry (AC) comprises at least two two-operand arithmetic units (AUl - AU3), each for calculating an addition and/or a subtraction of two operands being a first and a second binary number, and overflow and saturation means (OSUl - OSU3) for detecting a calculation overflow of at least one two-operand arithmetic unit (AUl - AU3) and for saturating the calculation result of the arithmetic unit (AUl - AU3) in accordance with the detected overflow result.

4. 发明申请

WO2004025453A8 APPARATUS AND METHOD FOR ADDING MULTIPLE-BIT BINARY STRINGS 审中-公开
标题翻译：用于添加多位二进制字符串的装置和方法
公开(公告)号：WO2004025453A8
公开(公告)日：2004-07-29
申请号：PCT/US0328393
申请日：2003-09-09
申请人： ANALOG DEVICES INC
发明人： JALFON MICHEL
IPC分类号： G06F7/50 , G06F7/509
CPC分类号： G06F7/509 , G06F7/4991
摘要： Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising : a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second adder for adding a portion of bits of the first output, the second adder being operable to add a plurality of m-bit addends, m being smaller than or equal to n. The apparatus further comprising at least two electronic-circuits, operatively associated with the first adder and the second adder. The first adder, the second adder and the at least two electronic-circuits are constructed and designed to obtain the value, the overflow status and a sign of the addition of the at least three data inputs, using predetermined parity rules being associated with a parity characteristic of the at least three data inputs.
摘要翻译：用于确定添加至少三个n位数据输入的值，符号和溢出状态的装置。所述设备包括：第一加法器，用于添加所述至少三个n位数据输入，以提供具有至少2n位的第一输出; 第二加法器，用于添加第一输出的一部分比特，第二加法器可操作以添加多个m比特加数，m小于或等于n。该设备还包括至少两个电子电路，其与第一加法器和第二加法器可操作地相关联。第一加法器，第二加法器和至少两个电子电路被构造和设计成使用与奇偶校验相关联的预定奇偶校验规则来获得值，溢出状态和至少三个数据输入的相加的符号至少三个数据输入的特征。

5. 发明申请

WO01046795A2 METHOD AND APPARATUS FOR PERFORMING SINGLE-CYCLE ADDITION OR SUBTRACTION AND COMPARISON IN REDUNDANT FORM ARITHMETIC 审中-公开
标题翻译：用于执行单周期添加或减少的冗余方法和比较方法
公开(公告)号：WO01046795A2
公开(公告)日：2001-06-28
申请号：PCT/US2000/042165
申请日：2000-11-13
IPC分类号： G06F7/02 , G06F7/48 , G06F7/50 , G06F7/509 , G06F7/38
CPC分类号： G06F7/5095 , G06F7/02 , G06F7/4824
摘要： A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic oepration is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.
摘要翻译：公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，还可以减去以冗余形式接收的数字，包括从旁路电路接收的数字。然后使用非传播比较器电路将给定值与运算电路的结果进行比较，以确定结果是否等于给定值。可以在整个电路中不传播进位信号来实现上述所有操作。该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。它还包括向算术电路提供调整输入以增加通过运算电路产生的结果。如果算术运算是减法运算，则该调整将使运算电路产生冗余形式的有效结果作为减法运算的结果。然后将结果与使用非传播比较器的给定值进行比较，以确定结果与给定值的相等或不等式。

6. 发明申请

WO2023064825A1 ACCUMULATOR FOR DIGITAL COMPUTATION-IN-MEMORY ARCHITECTURES 审中-公开
公开(公告)号：WO2023064825A1
公开(公告)日：2023-04-20
申请号：PCT/US2022/077994
申请日：2022-10-12
申请人： QUALCOMM INCORPORATED
发明人： BADAROGLU, Mustafa , WANG, Zhongze
IPC分类号： G06F7/509 , G06F7/60 , G06F7/544 , G06F17/00 , G06N3/00
摘要： Certain aspects relate to performing machine learning tasks, and in particular, to computation-in-memory (CIM) architectures. One aspect provides a method for in-memory computation. The method generally includes: accumulating, via each digital counter of a plurality of digital counters, output signals on a respective column of multiple columns of a memory, wherein a plurality of memory cells are on each of the multiple columns, the plurality of memory cells storing multiple bits representing weights of a neural network, wherein the plurality of memory cells of each of the multiple columns correspond to different word-lines of the memory; adding, via an adder circuit, output signals of the plurality of digital counters; and accumulating, via an accumulator, output signals of the adder circuit.

7. 发明申请

WO2020081916A1 OPTIMIZATION OF NEURAL NETWORKS USING HARDWARE CALCULATION EFFICIENCY AND ADJUSTMENT FACTORS 审中-公开
公开(公告)号：WO2020081916A1
公开(公告)日：2020-04-23
申请号：PCT/US2019/056905
申请日：2019-10-18
申请人： FACEBOOK, INC.
发明人： JOHNSON, Jeffrey, Hoyle
IPC分类号： G06F7/483 , G06F7/509
摘要： In one embodiment, a method includes receiving a request for an operation to be performed; determining that the operation is associated with a machine-learning algorithm, and in response, route the operation to a computing circuit; performing, at the computing circuit, the operation, including: determining a linear domain product of a first log-domain number and a second log-domain number associated with the operation based on a summation of the first log- domain number and the second log-domain number and output a third log-domain number approximating the linear domain product of the first log-domain number and the second log- domain number; converting the third log-domain number to a first linear-domain number; summing the first linear-domain number and a second linear-domain number associated with the operation, and output a third linear-domain number as the summed result.

8. 发明申请

WO02071203A3 7 TO 3 BIT CARRY-SAVE ADDER 审中-公开
标题翻译： 7-TO-3位进位保存加法器
公开(公告)号：WO02071203A3
公开(公告)日：2003-04-03
申请号：PCT/DE0200656
申请日：2002-02-22
申请人： INFINEON TECHNOLOGIES AG , HATSCH JOEL , KOEPPE SIEGMAR , LACKERSCHMID EVA , KAMP WINFRIED , KUENEMUND RONALD , SOELDNER HEINZ
发明人： HATSCH JOEL , KOEPPE SIEGMAR , LACKERSCHMID EVA , KAMP WINFRIED , KUENEMUND RONALD , SOELDNER HEINZ
IPC分类号： G06F7/50 , G06F7/509 , G06F7/60
CPC分类号： G06F7/509 , G06F7/5016 , G06F7/607 , G06F2207/3872
摘要： A carry-save adder for adding up bits having the same significance, comprising seven inputs (i0, i1, ..., i6) receiving seven bits having respectively the same significance w for the addition thereof. w. The adder has an output (s) for a sum bit of significance w, in addition to two outputs (c1, c2) for two transfer bits of significance 2w and 4w.
摘要翻译：为总结的意义相同比特的进位加法器保存有七个输入（I0，I1，...，I6）以接受七位即可概括每个都具有同样的意义W上。加法器具有用于权重的总和位W和两个输出端（C1，C2），用于化合价的2个位位和2瓦特4瓦特输出（一个或多个）。

9. 发明申请

WO2023085442A1 고정확도 딥러닝 연산 장치 审中-公开
公开(公告)号：WO2023085442A1
公开(公告)日：2023-05-19
申请号：PCT/KR2021/016178
申请日：2021-11-09
申请人： 한국전자기술연구원
发明人： 이상설 , 박종희 , 장성준 , 성민용
IPC分类号： G06N3/063 , G06N3/08 , G06F7/498 , G06F7/53 , G06F7/509
摘要： 고정확도 딥러닝 연산 장치가 제공된다. 본 발명의 실시예에 따른 Adder Tree 연산 장치는, 제1 데이터를 입력받는 제1 레지스터, 제2 데이터를 입력받는 제2 레지스터, 제1 데이터의 exponent와 제2 데이터의 exponent를 비교하는 비교기, 비교기의 비교 결과를 기초로 제1 데이터와 제2 데이터 중 하나는 변환기로 전달하고 다른 하나는 버퍼로 전달하는 스위치, 전달되는 데이터의 exponent를 변환하는 변환기, 전달되는 데이터를 저장하였다가 그대로 출력하는 버퍼 및 변환기에서 출력되는 데이터와 버퍼에서 출력되는 데이터를 덧셈하는 덧셈기를 포함한다. 이에 의해, Adder Tree 연산에서 덧셈할 두 데이터의 exponent를 더 작은 exponent로 변환하여 덧셈함으로써, 연산에 필요한 메모리를 획기적으로 줄여, 리소스에 제한이 있는 디바이스의 딥너링 가속장치에서도 문제 없는 Adder Tree 연산을 가능하게 한다.

10. 发明申请

WO2006128074A1 SYSTEM AND METHOD OF PERFORMING TWO’S COMPLEMENT OPERATIONS IN A DIGITAL SIGNAL PROCESSOR 审中-公开
标题翻译：在数字信号处理器中执行两次补充操作的系统和方法
公开(公告)号：WO2006128074A1
公开(公告)日：2006-11-30
申请号：PCT/US2006/020635
申请日：2006-05-25
申请人： QUALCOMM INCORPORATED , KRITHIVASAN, Shankar , KOOB, Christopher Edward
发明人： KRITHIVASAN, Shankar , KOOB, Christopher Edward
IPC分类号： G06F7/509
CPC分类号： G06F7/509 , G06F7/544 , G06F2207/5442
摘要： A method of completing a two's complement operation includes receiving a plurality of byte values and splitting the plurality of byte values into a first portion and a second portion. Further, the method includes inputting the first portion to a first segment of a first four-to-two compressor, performing a first four-to-two compression operation on the first portion to generate a first set of results having a first row and a second row that is offset one bit from the first row, and carrying in a first value of one to complete a first two's complement operation. The method also includes inputting the second portion to a second segment of a second four-to-two compressor and adding two values of one immediately to the right of the second portion in order to carry in a second value of one to the second portion to complete a second two's complement operation.
摘要翻译：完成二进制补码操作的方法包括接收多个字节值并将多个字节值分割成第一部分和第二部分。此外，所述方法包括将第一部分输入到第一四对二压缩机的第一段，对第一部分执行第一四到二压缩操作，以产生具有第一行和第二部分的第一组结果第二行与第一行偏移一位，并携带第一个值，以完成前两个补码操作。该方法还包括将第二部分输入到第二四对二压缩机的第二部分，并且立即将第二部分的第二部分加到第二部分的右侧，以便将第二部分的第二部分加到第二部分的第二部分完成二分之二的补充操作。

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