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1. 发明申请

WO2022012216A1 DNA活字存储系统和方法审中-公开
公开(公告)号：WO2022012216A1
公开(公告)日：2022-01-20
申请号：PCT/CN2021/098663
申请日：2021-06-07
申请人：中国科学院北京基因组研究所（国家生物信息中心）
发明人：陈非 , 卜东波 , 马灌楠 , 王晨阳 , 邢晶
IPC分类号： G06F16/172 , G06F16/174 , H03M7/06 , G16B50/00
摘要：一种DNA活字存储系统和方法，该方法包括提供内容活字实物库和索引活字实物库；将目标文件中的待储存数据拆分为多个数据元素，并针对各数据元素标注索引信息，将数据元素的内容信息对应至内容活字实物库中的特定内容活字寡核苷酸片段，将索引信息对应至索引活字实物库中的特定索引活字寡核苷酸片段；然后，将内容活字寡核苷酸片段和索引活字寡核苷酸片段连接构成DNA活字单元，由多个DNA活字单元构成保存有全部待储存数据元素的DNA存储文件。其中的DNA活字实物库可一次合成，多次重复使用，自由组合，极大降低DNA合成成本，且可以避免多次设计及合成DNA片段的人工与时间投入，并避免引入大量纠错序列所带来的成本负担。

2. 发明申请

WO02009281A2 5-ARY RECEIVER UTILIZING COMMON MODE INSENSITIVE DIFFERENTIAL OFFSET COMPARATOR 审中-公开
标题翻译： 5-ARY接收机使用通用模式无差异偏移比较器
公开(公告)号：WO02009281A2
公开(公告)日：2002-01-31
申请号：PCT/EP2001/008400
申请日：2001-07-19
IPC分类号： H03K5/08 , H03K5/1532 , H03M7/00 , H03M7/06 , H04L25/02 , H03K
CPC分类号： H04L25/0292 , H03M7/00 , H03M7/06 , H04L25/0274
摘要： A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage. The timing recovery circuitry is configured to receive the differential output voltages from each of the differential comparators and is operative to derive a clock via edge detection and generate a recovered clock signal. The signal conversion circuitry is coupled with the timing recovery circuitry and the differential comparators and is operative to convert the differential output voltages into a binary equivalent. A method is also provided.
摘要翻译：提供信号转换器，用于将多电平编码的数字信号转换为二进制等效信号。信号转换器包括参考电压发生器，多个四输入差分比较器，定时恢复电路和信号转换电路。参考电压发生器用于产生多个逐渐变大的差分参考电压。多个差分比较器各自用于将差分输入电压的幅度与逐渐变大的差分参考电压中的专用差分输入电压的幅度进行比较，并且如果差分输入电压的幅度更大则产生具有第一逻辑检测的差分输出电压如果差分输入电压的幅度小于差分参考电压的幅度，则具有第二逻辑检测。每个比较器具有偏移输入电压。定时恢复电路被配置为从每个差分比较器接收差分输出电压，并且可操作以经由边沿检测导出时钟并产生恢复的时钟信号。信号转换电路与定时恢复电路和差分比较器耦合，并且可操作地将差分输出电压转换为二进制等效。还提供了一种方法。

3. 发明申请

WO2005119919A2 TRI-VALUE DECODER CIRCUIT AND METHOD 审中-公开
标题翻译：三值解码器电路和方法
公开(公告)号：WO2005119919A2
公开(公告)日：2005-12-15
申请号：PCT/US2005019831
申请日：2005-06-06
申请人： TEXAS INSTRUMENTS INC , STULIK PAUL , CHEUNG HUGO
发明人： STULIK PAUL , CHEUNG HUGO
IPC分类号： H03M1/36 , H03M1/38 , H03M7/00 , H03M7/06
CPC分类号： H03M1/38 , H03M7/06
摘要： A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid-rail value for tri-state detection, and with less dependence on variations in product, process and temperature. An exemplary tri-value decoder circuit comprises a switch circuit 402, a feedback loop 404 and a sequence detector 406. Switch circuit 402 includes a pull-up switch MP and a pull-down switch MN, with optional current-limiting resistors, controlled by an output Q of a flip-flop 408 of feedback loop 404 to provide a sampled sequence of the tri-state input signal to the sequence detector 406. Sequence detector 406 decodes the tri-state input signal into a two-bit digital signal by detecting at least two samples of the tri-state input signal during a sampling period.
摘要翻译：提供了三值解码器和用于解码输入信号的至少三种状态的方法。示例性三值解码器和方法可以有助于解码输入信号而不使用阈值和/或强制三态输入信号到三态检测的中间轨值，并且对产品变化的依赖性较小，工艺和温度。示例性三值解码器电路包括开关电路402，反馈环路404和序列检测器406.开关电路402包括上拉开关MP和下拉开关MN，其中可选的限流电阻由反馈回路404的触发器408的输出Q，以向该序列检测器406提供三态输入信号的采样序列。序列检测器406通过检测将三态输入信号解码为2位数字信号在采样周期内，三态输入信号的至少两个样本。

4. 发明申请

WO2007125366A3 DIGITAL-TO-ANALOGUE CONVERTERS 审中-公开
公开(公告)号：WO2007125366A3
公开(公告)日：2007-11-08
申请号：PCT/GB2007/050217
申请日：2007-04-26
申请人： ARTIMI INC , CARROLL, Brian Stephen
发明人： CARROLL, Brian Stephen
IPC分类号： H03M5/18 , H03M7/06 , H04L25/49 , H03M1/68
摘要： Digital-to-Analogue Converters This invention generally relates to digital-to-analogue converters (DACs). More particularly it relates to differential, current-steering DACs with reduced small signal differential non-linearity. A differential current-steering digital-to-analogue converter (DAC), the DAC comprising: a digital input to receive a binary code comprising a plurality of bits defining a signed digital value for conversion into a signed differential analogue output signal; a pair of differential analogue output lines to provide said differential analogue output; and a set of binary-weighted steerable substantially constant current generators each coupled to said differential output lines and having a control input to receive a signal derived from said digital input to control current steering to said differential output lines responsive to said binary input code; wherein a said steerable substantially constant current generator comprises a ternary substantially constant current generator configured to generate a three-state differential current in response to a ternary signal on said control input; wherein each of said ternary current generators is associated with a bit of said binary code; and wherein said DAC further comprises a code converter coupled between said DAC digital input and said control inputs of said steerable current generators to convert said binary input code to a ternary code to control said steerable current generators.

5. 发明申请

WO99008264A1 DATA STORAGE SYSTEM HAVING EFFICIENT BLOCK CODE IMPLEMENTATION 审中-公开
标题翻译：具有有效的块代码实现的数据存储系统
公开(公告)号：WO99008264A1
公开(公告)日：1999-02-18
申请号：PCT/US1998/009814
申请日：1998-05-14
IPC分类号： G11B5/012 , G11B5/09 , G11B20/14 , H03M7/14 , H04L25/49 , G06F13/32 , G11B5/02 , H03M7/06
CPC分类号： G11B5/012 , G11B5/09 , G11B20/1426 , G11B2020/1446
摘要： A storage device (100) includes a storage medium (102), write element (108) and a data input (112). A first encoder (152) provides an encoded data output as a function of a first portion of the data input (112). The first encoder (152) also provides a state output (156). A second encoder (154) provides a second encoded data output as a function of a portion of data input (112) and as a function of the state output (156). The first and second data outputs are coupled to the write element (108) for writing information onto the storage medium (102). In addition, a similar technique is used for a block decoder (134).
摘要翻译：存储设备（100）包括存储介质（102），写入元件（108）和数据输入（112）。第一编码器（152）提供作为数据输入（112）的第一部分的函数的编码数据输出。第一编码器（152）还提供状态输出（156）。第二编码器（154）提供作为数据输入（112）的一部分并且作为状态输出（156）的函数的函数的第二编码数据输出。第一和第二数据输出耦合到写元件（108），用于将信息写入存储介质（102）。此外，类似的技术用于块解码器（134）。

6. 发明申请

WO2007125366A2 DIGITAL-TO-ANALOGUE CONVERTERS 审中-公开
标题翻译：数字到模拟转换器
公开(公告)号：WO2007125366A2
公开(公告)日：2007-11-08
申请号：PCT/GB2007050217
申请日：2007-04-26
申请人： ARTIMI INC , CARROLL BRIAN STEPHEN
发明人： CARROLL BRIAN STEPHEN
IPC分类号： H03M5/18 , H03M1/68 , H03M7/06 , H04L25/49
CPC分类号： H04L25/4925 , H03M1/745 , H04L27/2626
摘要： Digital-to-Analogue Converters This invention generally relates to digital-to-analogue converters (DACs). More particularly it relates to differential, current-steering DACs with reduced small signal differential non-linearity. A differential current-steering digital-to-analogue converter (DAC), the DAC comprising: a digital input to receive a binary code comprising a plurality of bits defining a signed digital value for conversion into a signed differential analogue output signal; a pair of differential analogue output lines to provide said differential analogue output; and a set of binary-weighted steerable substantially constant current generators each coupled to said differential output lines and having a control input to receive a signal derived from said digital input to control current steering to said differential output lines responsive to said binary input code; wherein a said steerable substantially constant current generator comprises a ternary substantially constant current generator configured to generate a three-state differential current in response to a ternary signal on said control input; wherein each of said ternary current generators is associated with a bit of said binary code; and wherein said DAC further comprises a code converter coupled between said DAC digital input and said control inputs of said steerable current generators to convert said binary input code to a ternary code to control said steerable current generators.
摘要翻译：数模转换器本发明一般涉及数模转换器（DAC）。更具体地说，它涉及具有减小的小信号差分非线性的差分，电流导向DAC。一种差分电流转向数模转换器（DAC），该DAC包括：数字输入端，用于接收包含多个位的二进制码，该位定义用于转换为有符号差分模拟输出信号的带符号数字值; 一对差分模拟输出线，用于提供所述差分模拟输出; 以及一组二进制加权的可操作的恒定恒定电流发生器，每一个都耦合到所述差分输出线并具有一个控制输入端，用于接收从所述数字输入端导出的信号，以响应于所述二进制输入码来控制对所述差分输出线路的电流转向; 其特征在于，一个所述可操纵的基本恒定的电流发生器包括三元基本上恒定的电流发生器，其被配置为响应于所述控制输入上的三进制信号产生三态差动电流; 其中每个所述三进制电流发生器与所述二进制码的位相关联; 并且其中所述DAC还包括耦合在所述DAC数字输入和所述可控电流发生器的所述控制输入之间的代码转换器，以将所述二进制输入代码转换为三进制代码以控制所述可转向电流发生器。

7. 发明申请

WO0209281A3 5-ARY RECEIVER UTILIZING COMMON MODE INSENSITIVE DIFFERENTIAL OFFSET COMPARATOR 审中-公开
标题翻译： 5-ARY接收器利用通用模式不敏感差分偏置比较器
公开(公告)号：WO0209281A3
公开(公告)日：2002-06-06
申请号：PCT/EP0108400
申请日：2001-07-19
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： CICCONE JOHN , SESSIONS D C , LIEPOLD CARL
IPC分类号： H03K5/08 , H03K5/1532 , H03M7/00 , H03M7/06 , H04L25/02 , H04L25/49 , H03M1/00 , H03M5/20
CPC分类号： H04L25/0292 , H03M7/00 , H03M7/06 , H04L25/0274
摘要： A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage. The timing recovery circuitry is configured to receive the differential output voltages from each of the differential comparators and is operative to derive a clock via edge detection and generate a recovered clock signal. The signal conversion circuitry is coupled with the timing recovery circuitry and the differential comparators and is operative to convert the differential output voltages into a binary equivalent. A method is also provided.
摘要翻译：提供信号转换器用于将多个电平编码的数字信号转换为二进制等效信号。信号转换器包括参考电压发生器，多个四输入差分比较器，定时恢复电路和信号转换电路。参考电压发生器可操作以产生多个逐渐增大的差分参考电压。多个差分比较器各自用于将差分输入电压的大小与逐渐变大的差分参考电压中的专用一个的大小进行比较，并且如果差分输入电压的大小更大则产生具有第一逻辑感测的差分输出电压如果差分输入电压的幅度小于差分参考电压的幅度，则具有第二逻辑检测。每个比较器都有一个偏置输入电压。定时恢复电路被配置为从每个差分比较器接收差分输出电压，并且可操作用于经由边缘检测导出时钟并生成恢复的时钟信号。信号转换电路与定时恢复电路和差分比较器耦合，并且可操作地将差分输出电压转换成二进制等效。还提供了一种方法。

8. 发明申请

WO9322720A3 PROCESS FOR FINDING THE RECIPROCAL OF A DIVISOR BY STEPWISE APPROXIMATION 审中-公开
标题翻译：通过逐步逼近发现一个分支机构的过程
公开(公告)号：WO9322720A3
公开(公告)日：1994-03-31
申请号：PCT/AT9300074
申请日：1993-04-29
申请人： JOHANN KAMLEITHNER FA
发明人： VACARIU CORNELL
IPC分类号： G06F7/48 , G06F7/52 , H03M7/06 , G06F7/49
CPC分类号： G06F7/5332 , G06F7/4824 , G06F7/535 , G06F7/5375 , H03M7/06
摘要： A novel process and a pure hardware and architecturally symmetrical division circuit is described which recursively and bidirectionally finds a quotient from a dividend and a divisor by approximation. It is thus possible to start the calculation with the highest or lowest position value or at the same time with the two extremes of the divisor/divident/quotient, in a parallel process. The division circuit therefore consists of four parts, with two symmetrical pairs. The left-hand main circuit (1), which is symmetrical with the right-hand sub-circuit (3), processes the divisor and, via the two control signals D/I and AS, controls the left hand sub-circuit (2) which is symmetrical with the right-hand sub-circuit (4) and processes the dividend in order to find the quotient. The two symmetrical parts can operate mutually independently, i.e. separately, thus making it possible to perform two different division operations at the same time via the two symmetrical halves. The division process can thus be performed bidirectionally or on one side (left or right). The operands may be represented in a non-redundant format or in a digit format with a sign, where 'carry-ripple' transfer can be prevented by the representation strategy of the 'non-neighbouring non-zero trits' and a region centred on '1' will be alocated to the absolute value of the mantissa (M) after the standardisation process.

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