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1. 发明申请

WO2012003609A1 NORMALLY-OFF III-NITRIDE METAL-2DEG TUNNEL JUNCTION FIELD-EFFECT TRANSISTORS 审中-公开
标题翻译：正常关闭III-NITRIDE金属2DEG隧道连接场效应晶体管
公开(公告)号：WO2012003609A1
公开(公告)日：2012-01-12
申请号：PCT/CN2010/001373
申请日：2010-09-08
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY , CHEN, Jing , YUAN, Li , CHEN, Hongwei , ZHOU, Chunhua
发明人： CHEN, Jing , YUAN, Li , CHEN, Hongwei , ZHOU, Chunhua
IPC分类号： H01L29/778
CPC分类号： H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/7781 , H01L29/7786 , H01L29/7788 , H01L29/872 , H01L29/88 , H01L2224/06181 , H01L2924/12032 , H01L2924/13062 , H01L2924/00
摘要： Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures.
摘要翻译：提供了用于产生异质结AlGaN / GaN金属二维电子气（2DEG）隧道结场效应晶体管（TJ-FET）的结构，器件和方法。在一方面，金属2DEG肖特基隧道结可以用于能够进行常关断操作，大的击穿电压，低漏电流和高导通/截止电流比的III-N型氮化物场效应器件中。作为另外的优点，公开了可以以横向配置和/或垂直配置制造的AlGaN / GaN金属2DEG TJ-FET。提供了另外的非限制性实施例，其示出了所公开的结构的优点和灵活性。

2. 发明申请

WO2007062589A1 MONOLITHIC INTEGRATION OF ENHANCEMENT- AND DEPLETION-MODE AlGaN/GaN HFETS 审中-公开
标题翻译：增强型和分离型AlGaN / GaN HFETs的单晶集成
公开(公告)号：WO2007062589A1
公开(公告)日：2007-06-07
申请号：PCT/CN2006/003219
申请日：2006-11-29
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY , CHEN, Jing , CAI, Yong , LAU, Keimay
发明人： CHEN, Jing , CAI, Yong , LAU, Keimay
IPC分类号： H01L29/786
CPC分类号： H01L29/7787 , H01L21/8252 , H01L27/0605 , H01L29/2003 , H01L29/66462
摘要： A method for and devices utilizing monolithic integration of enhancement- mode and depletion-mode AlGaN/GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode HFETs are then defined. Gate electrodes of the enhancement-mode HFETs are then defined using fluoride-based plasma treatment and high temperature post-gate annealing of the sample. Device isolation is achieved by either mesa etching or fluoride-based plasma treatment. This method provides a complete planar process for GaN-based integrated circuits favored in high-density and high-speed applications.
摘要翻译：公开了利用增强型和耗尽型AlGaN / GaN异质结场效应晶体管（HFET）的单片集成的方法和器件。首先定义HFET的源极和漏极欧姆接触。然后限定耗尽型HFET的栅电极。然后使用基于氟化物的等离子体处理和样品的高温栅极退火来限定增强型HFET的栅电极。器件隔离通过台面蚀刻或基于氟化物的等离子体处理来实现。该方法为在高密度和高速应用中有利的基于GaN的集成电路提供了一个完整的平面工艺。

3. 发明申请

WO2015131846A1 P-DOPING-FREE SCHOTTKY-ON-HETEROJUNCTION LIGHT-EMITTING DIODE AND HIGH-ELECTRON-MOBILITY LIGHT-EMITTING TRANSISTOR 审中-公开
标题翻译：无掺杂的肖特基二极管发光二极管和高电子发光发光晶体管
公开(公告)号：WO2015131846A1
公开(公告)日：2015-09-11
申请号：PCT/CN2015/073753
申请日：2015-03-06
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： CHEN, Jing , LI, Baikui , WANG, Jiannong , TANG, Xi
IPC分类号： H01L27/15
CPC分类号： H01L27/15 , H01L29/2003 , H01L29/7787 , H01L33/0041
摘要： A p-doping-free Schottky-on-heterojunction light-emitting-diode (SoH-LED) and a high-electron-mobility light-emitting transistor (HEM-LET) including the SoH-LED and integration of HEMT and SoH-LED are described. In an aspect, a light emitting device structure is provided that includes a substrate and a p-doping free heterostructure including a channel layer formed on and adjacent to the substrate and comprising a material with a first bandgap, a barrier layer formed on and adjacent to the channel layer and comprising a material with a second bandgap larger than the first bandgap, and a two-dimensional electron gas (2DEG) channel formed at an interface between the channel layer and the barrier layer. The light emitting device structure further includes a Schottky anode electrode formed on and adjacent to the barrier layer, and an ohmic cathode electrode formed on and adjacent to the barrier layer and electrically coupled to the 2DEG layer.
摘要翻译：包含SoH-LED和HEMT和SoH-LED集成的高电子迁移率发光二极管（SoH-LED）和高电子迁移率发光晶体管（HEM-LET）的P型掺杂肖特基 - 异质结发光二极管被描述。在一方面，提供了一种发光器件结构，其包括衬底和p掺杂自由异质结构，其包括形成在衬底上并与衬底相邻的沟道层，并且包括具有第一带隙的材料，形成在其上并与之相邻的阻挡层所述沟道层包括具有大于所述第一带隙的第二带隙的材料，以及形成在所述沟道层和所述势垒层之间的界面处的二维电子气（2DEG）沟道。发光器件结构还包括形成在势垒层上并与阻挡层相邻的肖特基阳极电极和形成在阻挡层上并与阻挡层相邻并且电耦合到2DEG层的欧姆阴极电极。

4. 发明申请

WO2018036413A1 METAL-INSULATOR-SEMICONDUCTOR TRANSISTORS WITH GATE-DIELECTRIC/SEMICONDUCTOR INTERFACIAL PROTECTION LAYER 审中-公开
标题翻译：具有栅介电/半导体界面保护层的金属 - 绝缘体 - 半导体晶体管
公开(公告)号：WO2018036413A1
公开(公告)日：2018-03-01
申请号：PCT/CN2017/097646
申请日：2017-08-16
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： CHEN, Jing , HUA, Mengyuan
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L21/28264 , H01L29/2003 , H01L29/4236 , H01L29/513
摘要： Structures, devices and methods are provided for forming an interface protection layer (204) adjacent to a fully or partially recessed gate structure (202) of a group III nitride, a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) device or a metal-insulator-semiconductor field-effect transistor (MIS-FET) device, and forming a gate dielectric (114) disposed on the interface protection layer (204).
摘要翻译：提供了用于形成与III族氮化物的完全或部分凹陷的栅极结构（202）相邻的界面保护层（204），金属 - 绝缘体 - 半导体高温半导体材料的结构，器件和方法，电子迁移晶体管（MIS-HEMT）器件或金属 - 绝缘体 - 半导体场效应晶体管（MIS-FET）器件，并且形成设置在界面保护层（204）上的栅极电介质（114）。

5. 发明申请

WO2017190652A1 POWER DEVICE WITH INTEGRATED GATE DRIVER 审中-公开
标题翻译：带集成栅极驱动器的电源设备
公开(公告)号：WO2017190652A1
公开(公告)日：2017-11-09
申请号：PCT/CN2017/082833
申请日：2017-05-03
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： CHEN, Jing , TANG, Gaofei
IPC分类号： H02M1/08 , H03K17/687
摘要： A self-bootstrap integrated gate driver circuit with high driving speed, enhanced driving capability and rail-to-rail output. A capacitor (120) and a diode (118) are used with a first inverter (102) coupled to a control signal input terminal, a second inverter (104) coupled to the first inverter (102), a push-pull circuit (106) comprising a pull-up transistor (116) and a pull-down transistor (115) and a power device comprising a power device transistor (108) with a gate. The control signal input at one state controls the first inverter (102) to a first output state, turns on the pull-down transistor (115) to discharge the gate of the power device transistor (108), turns off the power device and charges the capacitor (120) through the diode (118). The control signal input in another state controls the first inverter (102) to a second output state, turns off the pull-down transistor (115) and turns on the pull-up transistor (116) via the capacitor (120) to turn on the power device.
摘要翻译：
具有高驱动速度，增强驱动能力和轨到轨输出的自引导集成栅极驱动器电路。电容器（120）和二极管（118）与耦合到控制信号输入端子的第一反相器（102），耦合到第一反相器（102）的第二反相器（104），推挽电路）包括上拉晶体管（116）和下拉晶体管（115）以及包括具有栅极的功率器件晶体管（108）的功率器件。在一个状态下的控制信号输入控制第一反相器（102）至第一输出状态，接通下拉晶体管（115）以使功率器件晶体管（108）的栅极放电，关断功率器件并对电荷进行充电电容器（120）通过二极管（118）。在另一个状态下输入的控制信号控制第一反相器（102）进入第二输出状态，关断下拉晶体管（115）并通过电容器（120）导通上拉晶体管（116）导通功率器件。

6. 发明申请

WO2016074642A1 TRANSISTORS HAVING ON-CHIP INTEGRARED PHOTON SOURCE OR PHOTONIC-OHMIC DRAIN TO FACILIATE DE-TRAPPING ELECTRONS TRAPPED IN DEEP TRAPS OF TRANSISTORS 审中-公开
标题翻译：具有片上整合的光子源或光子阱的晶体管可以用于捕获在深度深度的晶体管中的电子捕获电子
公开(公告)号：WO2016074642A1
公开(公告)日：2016-05-19
申请号：PCT/CN2015/094518
申请日：2015-11-13
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： CHEN, Jing , LI, Baikui , TANG, Xi
IPC分类号： H01L29/778 , H01L27/15
CPC分类号： H03K17/063 , H01L27/15 , H01L29/0657 , H01L29/1033 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/41725 , H01L29/7786 , H01L29/7787 , H01L33/0025 , H01L33/0033 , H01L33/32 , H01L33/36
摘要： Techniques are provided that pumping of deep traps in GaN electronic devices using photons from an on-chip photon source. In various embodiments, a method for optical pumping of deep traps in GaN HEMTs is provided using an on-chip integrated photon source that is configured to generate photons during operation of the HEMT. In an aspect, the on-chip photon source is a SoH-LED. In various additional embodiments, an integration scheme is provided that integrates the photon source into the drain electrode of a HEMT, thereby converting the conventional HEMT with an ohmic drain to a transistor with hybrid photonic-ohmic drain (POD), a POD transistor or PODFET for short.
摘要翻译：提供了使用来自片上光子源的光子在GaN电子器件中泵送深陷阱的技术。在各种实施例中，使用被配置为在HEMT的操作期间产生光子的片上集成光子源来提供用于光学泵浦GaN HEMT中的深陷阱的方法。在一方面，片上光子源是SoH-LED。在各种另外的实施例中，提供了将光子源集成到HEMT的漏电极中的集成方案，从而将具有欧姆漏极的常规HEMT转换为具有混合光子 - 欧姆漏极（POD），POD晶体管或PODFET 简而言之

7. 发明申请

WO2017000906A1 ENHANCEMENT-MODE DOUBLE-CHANNEL HIGH ELECTRON MOBILITY TRANSISTOR 审中-公开
标题翻译：增强型双通道高电子移动晶体管
公开(公告)号：WO2017000906A1
公开(公告)日：2017-01-05
申请号：PCT/CN2016/088062
申请日：2016-07-01
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： CHEN, Jing , WEI, Jin
IPC分类号： H01L29/778
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/517 , H01L29/66204 , H01L29/66462 , H01L29/7783 , H01L29/861
摘要： Enhancement-mode (E-mode) double-channel (DC) HEMTs are provided. In one embodiment a semiconductor device is provided that includes a substrate and a heterostructure formed on the substrate. The heterostructure can include a lower channel layer, an upper channel layer, an insertion layer formed between the lower channel layer and the upper channel layer, and one or more barrier layers formed on the upper channel layer. The semiconductor device further includes a recess formed within the one or more barrier layers and at least a first portion of the upper channel layer, a gate structure formed within the recess. In various implementations, the gate structure has a gate dielectric layer formed on and adjacent to a wall of the recess and a gate electrode formed on and adjacent to the electrode dielectric layer.
摘要翻译：提供增强型（E模式）双通道（DC）HEMT。在一个实施例中，提供了一种半导体器件，其包括衬底和形成在衬底上的异质结构。异质结构可以包括下沟道层，上沟道层，形成在下沟道层和上沟道层之间的插入层以及形成在上沟道层上的一个或多个势垒层。所述半导体器件还包括形成在所述一个或多个阻挡层内的凹部和所述上部沟道层的至少第一部分，形成在所述凹部内的栅极结构。在各种实施方案中，栅极结构具有形成在凹部的壁上并与其相邻的栅极电介质层和形成在电极介电层上并与电极介电层相邻的栅电极。

8. 发明申请

WO2023016549A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：WO2023016549A1
公开(公告)日：2023-02-16
申请号：PCT/CN2022/112079
申请日：2022-08-12
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： CHEN, Jing , ZHENG, Zheyang , ZHANG, Li
IPC分类号： H01L29/778 , H01L29/66
摘要： A semiconductor device includes a buffer layer, a barrier layer, a nitride-based semiconductor layer, an isolation layer, and a gate electrode. The barrier layer is disposed on the buffer layer. The nitride-based semiconductor layer is disposed on the barrier layer and has a channel region and a doped region abutting against each other. The isolation layer covers the nitride-based semiconductor layer. The isolation layer and doped channel region can exhibit a type-II energy band alignment (staggered gate stack). The gate electrode is disposed over the isolation layer and the nitride-based semiconductor layer.

9. 发明申请

WO2018033034A1 SEMICONDUCTOR DEVICE WITH HYBRID CHANNEL CONFIGURATION 审中-公开
标题翻译：具有混合通道配置的半导体器件
公开(公告)号：WO2018033034A1
公开(公告)日：2018-02-22
申请号：PCT/CN2017/097326
申请日：2017-08-14
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： CHEN, Jing , WEI, Jin
IPC分类号： H01L29/78 , H01L29/76 , H01L21/336
CPC分类号： H01L29/66068 , H01L29/0865 , H01L29/1033 , H01L29/1037 , H01L29/1095 , H01L29/41766 , H01L29/42376 , H01L29/7802 , H01L29/7816
摘要： A semiconductor device (100) as described herein includes a substrate (111), a drift layer (112) formed onto the substrate (111), a trench formed into the drift layer (112) at a first surface of the drift layer (112) opposite the substrate (111), wherein the trench extends into the drift layer (112) to a trench depth and defines respective sidewalls of a mesa region orthogonal to the first surface of the drift layer (112), respective planar body regions (113) positioned in the drift layer (112) at the trench surface, respective planar source regions (114) positioned in the drift layer (112) at the trench surface and encapsulated by the respective planar body regions (113), respective mesa body regions (103) positioned in the mesa structure at the first surface of the drift layer (112), and respective mesa source regions (104) positioned in the mesa structure at the first surface of the drift layer (112) and encapsulated by the respective mesa body regions (103).
摘要翻译：本文所述的半导体器件（100）包括衬底（111），形成在衬底（111）上的漂移层（112），形成在漂移层（112）中的沟槽所述漂移层（112）的与所述衬底（111）相对的第一表面，其中所述沟槽延伸到所述漂移层（112）中至沟槽深度并且限定与所述漂移层（112）的所述第一表面正交的台面区域的相应侧壁），位于沟槽表面处的漂移层（112）中的相应的平面本体区域（113），位于沟槽表面处的漂移层（112）中并且由相应的平面本体区域（位于漂移层（112）的第一表面处的台面结构中的相应台面本体区域（103）以及位于漂移层（112）的第一表面处的台面结构中的相应台面源极区域（104））并由相应的台面本体区域（103）封装。

10. 发明申请

WO2017071635A1 SEMICONDUCTOR DEVICE WITH III-NITRIDE CHANNEL REGION AND SILICON CARBIDE DRIFT REGION 审中-公开
标题翻译：具有III-氮化物沟道区和碳化硅漂移区的半导体器件
公开(公告)号：WO2017071635A1
公开(公告)日：2017-05-04
申请号：PCT/CN2016/103726
申请日：2016-10-28
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： CHEN, Jing , WEI, Jin
IPC分类号： H01L29/267 , H01L29/772 , H01L21/8232
CPC分类号： H01L29/267 , H01L21/8258 , H01L27/0605 , H01L27/085 , H01L29/0623 , H01L29/0646 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/207 , H01L29/4236 , H01L29/66462 , H01L29/7786 , H01L29/7788 , H01L29/808
摘要： Techniques are provided for forming a semiconductor device. In an aspect, a semiconductor device (100) is provided that includes a silicon carbide (SiC) structure (102) and a III-nitride structure (104). The SiC structure includes a drain electrode (106), a substrate layer (108) that is formed on the drain electrode and includes SiC, and a drift layer (110) formed on the substrate layer. The drift layer includes p-well regions (112a, 112b) that allow current to flow through a region (134) between the p-well regions. The III-nitride structure includes a set of III-nitride semiconductor layers formed on the SiC structure, a passivation layer (1608) formed on the set of III-nitride semiconductor layers, a source electrode (126) electrically coupled to the p-well regions, and gate electrodes (1606a, 1606b) electrically isolated from the set of III-nitride semiconductor layers. In an aspect, the SiC structure includes a transition layer (111) that includes connecting regions (114a, 114b). In another aspect, the III-nitride structure includes connection electrodes (130a, 130b) electrically coupled to the connecting regions.
摘要翻译：提供了用于形成半导体器件的技术。一方面，提供了一种半导体器件（100），其包括碳化硅（SiC）结构（102）和III族氮化物结构（104）。 SiC结构包括漏电极（106），形成在漏电极上并包括SiC的衬底层（108）以及形成在衬底层上的漂移层（110）。漂移层包括允许电流流过p阱区之间的区域（134）的p阱区（112a，112b）。 III族氮化物结构包括形成在SiC结构上的一组III族氮化物半导体层，形成在该组III族氮化物半导体层上的钝化层（1608），电耦合到该p阱的源极（126）区域以及与该组III族氮化物半导体层电隔离的栅电极（1606a，1606b）。在一个方面，SiC结构包括包含连接区域（114a，114b）的过渡层（111）。在另一方面，III族氮化物结构包括电连接至连接区域的连接电极（130a，130b）。

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