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1. 发明申请

WO2013066583A3 A LOW VOLTAGE, LOW POWER BANDGAP CIRCUIT 审中-公开
公开(公告)号：WO2013066583A3
公开(公告)日：2013-05-10
申请号：PCT/US2012/059617
申请日：2012-10-10
申请人： SILICON STORAGE TECHNOLOGY, INC. , TRAN, Hieu, Van , LY, Anh , VU, Thuan , NGUYEN, Hung, Quoc
发明人： TRAN, Hieu, Van , LY, Anh , VU, Thuan , NGUYEN, Hung, Quoc
IPC分类号： G05F1/10 , G05F3/02
摘要： A bandgap voltage generating circuit for generating a bandgap voltage has an operational amplifier that has two inputs and an output. A current mirror circuit has at least two parallel current paths. Each of the current paths is controlled by the output from the operational amplifier. One of the current paths is coupled to one of the two inputs to the operational amplifier. A resistor divide circuit is connected to the other current path. The resistor divide circuit provides the bandgap voltage of the circuit.

2. 发明申请

WO2013085676A1 A NON-VOLATILE MEMORY DEVICE AND A METHOD OF PROGRAMMING SUCH DEVICE 审中-公开
标题翻译：非易失性存储器件和编程这种器件的方法
公开(公告)号：WO2013085676A1
公开(公告)日：2013-06-13
申请号：PCT/US2012/064881
申请日：2012-11-13
申请人： SILICON STORAGE TECHNOLOGY, INC. , TRAN, Hieu, Van , NGUYEN, Hung, Quoc , LY, Anh , VU, Thuan
发明人： TRAN, Hieu, Van , NGUYEN, Hung, Quoc , LY, Anh , VU, Thuan
IPC分类号： G11C11/00
CPC分类号： G11C16/10 , G11C7/00 , G11C7/22 , G11C16/26 , G11C16/28 , G11C2207/2263 , G11C2211/5647 , H01L27/11517
摘要： A non-volatile memory device has a charge pump for providing a programming current and aft array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.
摘要翻译：非易失性存储器件具有用于提供非易失性存储器单元的编程电流和后排阵列的电荷泵。阵列的每个存储单元都由来自电荷泵的编程电流编程。非易失性存储器单元的阵列被分割成多个单元，每个单元包括多个存储器单元。指示器存储单元与每个单位的非易失性存储单元相关联。编程电路使用编程电流来对每个单元的存储器单元进行编程，当每个单元的存储单元的百分之五十或更少被编程时，编程每个单元的存储器单元的反相和与每个单元使用编程电流时，每个单元的存储单元的百分之五十以上将被编程。

3. 发明申请

WO2013066592A2 A MIXED VOLTAGE NON-VOLATILE MEMORY INTEGRATED CIRCUIT WITH POWER SAVING 审中-公开
标题翻译：具有节电功能的混合电压非易失性存储器集成电路
公开(公告)号：WO2013066592A2
公开(公告)日：2013-05-10
申请号：PCT/US2012/059808
申请日：2012-10-11
申请人： SILICON STORAGE TECHNOLOGY, INC. , TRAN, Hieu, Van , LY, Anh , VU, Thuan , NGUYEN, Hung, Quoc
发明人： TRAN, Hieu, Van , LY, Anh , VU, Thuan , NGUYEN, Hung, Quoc
IPC分类号： G11C5/14 , G05F3/02
CPC分类号： G11C16/30 , G11C5/147 , G11C11/5628 , G11C16/08
摘要： An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.
摘要翻译：集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。第二电压小于第一电压。可在第一电压下操作的第一电路在集成电路管芯中。可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。检测来自第二管芯焊盘的电流的电路在集成电路管芯中。开关被插入在第一管芯焊盘和第一电路之间，以响应于用于检测电流的电路检测到的电流来将第一管芯焊盘与第一电路断开。

4. 发明申请

WO2013066584A1 A METHOD OF PROGRAMMING A SPLIT GATE NON-VOLATILE FLOATING GATE MEMORY CELL HAVING A SEPARATE ERASE GATE 审中-公开
标题翻译：一种具有单独擦除闸门的分离栅非易失性浮选槽存储单元的编程方法
公开(公告)号：WO2013066584A1
公开(公告)日：2013-05-10
申请号：PCT/US2012/059623
申请日：2012-10-10
申请人： SILICON STORAGE TECHNOLOGY, INC. , MARKOV, Viktor , YOO, Jong-Won , NGUYEN, Hung, Quoc , KOTOV, Alexander
发明人： MARKOV, Viktor , YOO, Jong-Won , NGUYEN, Hung, Quoc , KOTOV, Alexander
IPC分类号： G11C11/34
CPC分类号： G11C16/0416 , G11C16/3418 , H01L21/28273 , H01L29/42328
摘要： During the programming of a non-volatile memory cell, a voltage pulse is applied to an erase gate of the cell a delay time after voltage pulses are applied to the other elements of the cell. The erase gate voltage pulse ends at substantialy the same time as the other voltage pulses end.
摘要翻译：在非易失性存储单元的编程期间，电压脉冲施加到单元的其它元件的电压脉冲施加到单元的擦除栅极上的延迟时间。擦除栅极电压脉冲在其他电压脉冲结束的同时终止。

5. 发明申请

WO2017151296A1 MULTI-STEP VOLTAGE FOR FORMING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELL FILAMENT 审中-公开
标题翻译：形成电阻式随机存取存储器（RRAM）细胞丝的多级电压
公开(公告)号：WO2017151296A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/017543
申请日：2017-02-10
申请人： SILICON STORAGE TECHNOLOGY, INC. , AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
发明人： ZHOU, Feng , LIU, Xian , TRAN, Hieu, Van , NGUYEN, Hung, Quoc , DO, Nhan , REITEN, Mark , CHEN, Zhixian , XINPENG, Wang , LO, Guo-Qiang
IPC分类号： H01L45/00 , G11C11/00 , G11C11/02 , G11C13/00
摘要： A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.
摘要翻译：包括设置在第一和第二导电电极之间并与之电接触的金属氧化物材料的存储器件和方法，以及配置成施加跨越第一和第二导电电极的第一和第二导电电极之间的多个电压脉冲的电压源和第二电极。对于每一个电压脉冲，电压脉冲期间电压的幅度都会增加。

6. 发明申请

WO2016022275A1 FLASH MEMORY SYSTEM WITH EEPROM FUNCTIONALITY 审中-公开
标题翻译：具有EEPROM功能的闪存系统
公开(公告)号：WO2016022275A1
公开(公告)日：2016-02-11
申请号：PCT/US2015/041035
申请日：2015-07-17
申请人： SILICON STORAGE TECHNOLOGY, INC.
发明人： TRAN, Hieu, Van , NGUYEN, Hung, Quoc , DO, Nhan , TIWARI, Vipin
IPC分类号： G11C16/16 , G11C16/04 , G11C7/18
CPC分类号： G11C16/0433 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0425 , G11C16/0483 , G11C16/08 , G11C16/102 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , H01L27/11524 , H01L29/42328
摘要： The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.
摘要翻译：本发明涉及具有EEPROM功能的闪速存储器件。闪存器件是字节可擦除和位可编程的。

7. 发明申请

WO2014158311A1 DYNAMIC PROGRAMMING OF ADVANCED NANOMETER FLASH MEMORY 审中-公开
标题翻译：高级纳米闪存存储器动态编程
公开(公告)号：WO2014158311A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/011547
申请日：2014-01-14
申请人： SILICON STORAGE TECHNOLOGY, INC.
发明人： TRAN, Hieu, Van , LY, Anh , VU, Thuan , NGUYEN, Hung, Quoc
IPC分类号： G11C16/10 , G11C16/30
CPC分类号： G11C16/12 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/30
摘要： An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed, in which each of a set of mirrored current sources (110, 111, 112, 113) is connected in rotation to one of a corresponding set of bitlines (160, 170, 180, 190) via sets of switches (120-123, 130-133, 140-143, 150-153). This results in the time-averaged programming current supplied to each bitline being the same and reduces variation in programming current due to e.g. process variation in fabricating the transistors forming the mirrored current sources (110-113).
摘要翻译：公开了用于编程高级纳米闪速存储器单元的改进的方法和装置，其中一组镜像电流源（110,111,112,113）中的每一个旋转连接到相应的一组位线（160,170）中的一个，180,190）经由一组开关（120-123,130-133,140-143,150-153）。这导致提供给每个位线的时间平均编程电流相同并且减少由于例如电流而导致的编程电流的变化。制造形成镜像电流源（110-113）的晶体管的工艺变化。

8. 发明申请

WO2014077980A1 THREE-DIMENSIONAL FLASH MEMORY SYSTEM 审中-公开
标题翻译：三维闪存系统
公开(公告)号：WO2014077980A1
公开(公告)日：2014-05-22
申请号：PCT/US2013/063990
申请日：2013-10-09
申请人： SILICON STORAGE TECHNOLOGY, INC.
发明人： TRAN, Hieu, Van , NGUYEN, Hung, Quoc , REITEN, Mark
IPC分类号： G11C5/02 , G11C5/06 , G11C16/30 , H01L21/768 , H01L23/48 , H01L25/065 , H01L25/00 , G11C29/26
CPC分类号： G11C29/76 , G11C5/02 , G11C5/06 , G11C7/04 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C29/021 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/26 , G11C2213/71 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A three-dimensional flash memory system is disclosed.
摘要翻译：公开了三维闪存系统。

9. 发明申请

WO2014062435A1 NON-VOLATILE MEMORY ARRAY AND METHOD OF USING SAME FOR FRACTIONAL WORD PROGRAMMING 审中-公开
标题翻译：非易失性存储器阵列和使用相同字段编程的方法
公开(公告)号：WO2014062435A1
公开(公告)日：2014-04-24
申请号：PCT/US2013/064013
申请日：2013-10-09
申请人： SILICON STORAGE TECHNOLOGY, INC.
发明人： TRAN, Hieu, Van , LY, Anh , VU, Thuan , NGUYEN, Hung, Quoc
IPC分类号： G11C16/10 , G11C16/08 , G11C8/08 , G11C5/14 , G11C11/56
CPC分类号： G11C5/145 , G11C8/08 , G11C11/5628 , G11C16/08 , G11C16/10
摘要： A non-volatile memory device that includes N planes (102a, 102b) of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells (10) includes a plurality of memory cells configured in rows (22) and columns (20). Each of the N planes includes gate lines (26, 14, 28) that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.
摘要翻译：一种非易失性存储器件，其包括非易失性存储器单元的N个平面（102a，102b）（其中N是大于1的整数）。非易失性存储单元（10）的每个平面包括以行（22）和列（20）配置的多个存储单元。 N平面中的每一个包括跨越其中的存储单元的行延伸但不延伸到非易失性存储单元的N个平面中的其他平面的栅极线（26,14,28）。控制器被配置为将多个数据字中的每一个分成N个小数字，并且将每个数据字的N个分数字中的每一个分解成非易失性存储单元的N个平面中的不同的一个。控制器使用编程电流和编程时间段进行编程，并且可以配置为通过一个因素改变编程电流，并通过因子反向改变程序时间段。

10. 发明申请

WO2016053607A1 A NON-VOLATILE SPLIT GATE MEMORY DEVICE AND A METHOD OF OPERATING SAME 审中-公开
标题翻译：非挥发性分隔栅存储器件及其操作方法
公开(公告)号：WO2016053607A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/050010
申请日：2015-09-14
申请人： SILICON STORAGE TECHNOLOGY, INC.
发明人： TRAN, Hieu, Van , NGUYEN, Hung, Quoc , DO, Nhan
IPC分类号： G11C16/04 , G11C16/12
CPC分类号： G11C16/24 , G11C16/0408 , G11C16/0425 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26
摘要： A non- volatile memory device that a semiconductor substrate of a first conductivity type. An array of non- volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.
摘要翻译：一种非易失性存储器件，其是第一导电类型的半导体衬底。非易失性存储单元的阵列位于配置成多行和列的半导体衬底中。每个存储单元包括第二导电类型的半导体衬底的表面上的第一区域和第二导电类型的半导体衬底的表面上的第二区域。沟道区域在第一区域和第二区域之间。字线覆盖在沟道区域的第一部分上，并且与第一区域绝缘，并且与第一区域相邻并且与第一区域几乎没有或没有重叠。浮动栅极覆盖沟道区域的第二部分，与第一部分相邻，并与第二部分绝缘并与第二区域相邻。耦合栅极覆盖浮栅。位线连接到第一区域。负电荷泵电路产生第一负电压。控制电路接收指令信号并响应于此产生多个控制信号，并将第一负电压施加到未选择存储单元的字线。在程序操作期间，读取或擦除时，可以对未选择的存储单元的字线施加负电压。

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