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1. 发明申请

WO2016022319A2 PROTECTIVE MATERIAL TO PREVENT SHORT CIRCUITS IN THREE-DIMENSIONAL MEMORY DEVICE 审中-公开
标题翻译：防止三维存储设备中的短路的保护材料
公开(公告)号：WO2016022319A2
公开(公告)日：2016-02-11
申请号：PCT/US2015/042302
申请日：2015-07-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , PACHAMUTHU, Jayavel , DONG, Yingda , ZHAO, Wei
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , G01R31/025 , G11C16/0483 , G11C29/025 , H01L21/32136 , H01L21/76224 , H01L27/0255 , H01L27/0288 , H01L27/0629 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L28/20 , H01L28/40 , H01L29/16 , H01L29/42328 , H01L29/42344 , H01L29/6609 , H01L29/861
摘要： In a three-dimensional stacked non-volatile memory device, a short circuit is prevented in a select gate layer by providing a protective material such as a diode, capacitor, linear resistor or varistor between select gate lines and a remaining portion of the select gate layer. Charges which are accumulated in the select gate lines due to plasma etching are therefore prevented from discharging through the remaining portion in a short circuit path when the select gate lines are driven. The protective material can comprise a p-n diode, an n-i-n or p-i-p resistor, a thin oxide layer between doped polysilicon layers in a capacitor, or a variable-resistance material such as ZnO2 between oxide layers in a varistor.
摘要翻译：在三维堆叠式非易失性存储器件中，通过在选择栅极线之间提供诸如二极管，电容器，线性电阻器或变阻器之类的保护材料来防止选择栅极层中的短路和选择栅极层的剩余部分。因此，当选择栅极线被驱动时，由于等离子体蚀刻而累积在选择栅极线中的电荷被阻止通过短路路径中的剩余部分放电。保护材料可以包括p-n二极管，n-i-n或p-i-p电阻器，电容器中掺杂多晶硅层之间的薄氧化物层，或变阻器中氧化物层之间的可变电阻材料，例如ZnO2。

2. 发明申请

WO2016064514A1 DEUTERIUM ANNEAL OF SEMICONDUCTOR CHANNELS IN A THREE-DIMENSIONAL MEMORY STRUCTURE 审中-公开
标题翻译：三维存储器结构中半导体通道的绝缘子
公开(公告)号：WO2016064514A1
公开(公告)日：2016-04-28
申请号：PCT/US2015/051484
申请日：2015-09-22
申请人： SANDISK TECHNOLOGIES, INC.
发明人： ZHAO, Wei , DONG, Yingda , CHOWDHURY, Murshed , PACHAMUTHU, Jayavel , ALSMEIER, Johann
IPC分类号： H01L27/115 , H01L21/30
CPC分类号： H01L27/11556 , H01L21/223 , H01L21/3003 , H01L21/324 , H01L27/11582 , H01L29/04 , H01L29/16
摘要： A monolithic three-dimensional memory structure includes a memory stack structure including a memory film and a semiconductor channel. Traps and/or defects within the semiconductor channel and/or at the semiconductor/dielectric material interface and/or inside dielectric materials can be passivated by an anneal in a deuterium-containing gas, which replaces hydrogen atoms within the semiconductor channel or passivate the dangling bonds/traps with deuterium atoms. The anneal may be performed immediately after formation of the semiconductor channel, before or after formation of a dielectric core or a drain region, after replacement of sacrificial material layers with conductive material layers, after dicing of a substrate into semiconductor chips, or at another suitable processing step.
摘要翻译：单片三维存储器结构包括存储器堆叠结构，其包括存储器膜和半导体通道。半导体通道内和/或半导体/电介质材料界面和/或内部电介质材料内的陷阱和/或缺陷可以通过在含氘气中进行退火来钝化，该气体取代了半导体通道内的氢原子或钝化了悬空具有氘原子的键/陷阱。在将衬底切割成半导体芯片之后，或者在另一个合适的方法中，在用导电材料层替换牺牲材料层之后，可以在形成半导体沟道之后，在形成介电芯或漏极区之前或之后执行退火处理步骤。

3. 发明申请

WO2016022320A1 BIAS TO DETECT AND PREVENT SHORT CIRCUITS IN THREE-DIMENSIONAL MEMORY DEVICE 审中-公开
标题翻译：检测和预防三维存储器件中的短路电路
公开(公告)号：WO2016022320A1
公开(公告)日：2016-02-11
申请号：PCT/US2015/042305
申请日：2015-07-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , PACHAMUTHU, Jayavel , DONG, Yingda , ZHAO, Wei
IPC分类号： G11C16/24 , G11C29/02
CPC分类号： G11C16/10 , G11C7/12 , G11C16/24 , G11C16/26 , G11C29/021 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , H01L21/8221
摘要： In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit occurs when charges accumulated in select gate lines due to plasma etching, discharge through a the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates the bias exceeds a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit.
摘要翻译：在三维堆叠式非易失性存储器件中，检测并防止了选择栅极层中的短路。当选择栅极线由于等离子体蚀刻而累积的电荷在选择栅极线被驱动时通过选择栅极层在短路路径中放电而发生短路。为了检测短路，在测试阶段期间，当测量电流时，向剩余部分施加增加的偏差。高于阈值的电流增加表示偏压超过短路路径的击穿电压。此时的偏差值被记录为最佳偏差。在涉及选择栅晶体管或存储单元（例如编程，擦除或读取）的后续操作期间，当驱动选择栅极线以防止电流流过短路时施加最佳偏压。

4. 发明申请

WO2016003770A1 LOOK AHEAD READ METHOD FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：查看非易失性存储器的前瞻性读取方法
公开(公告)号：WO2016003770A1
公开(公告)日：2016-01-07
申请号：PCT/US2015/037805
申请日：2015-06-25
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , DONG, Yingda , ZHAO, Wei
IPC分类号： G11C11/56 , G11C16/26 , G11C16/34 , H01L27/115
CPC分类号： G11C16/34 , G11C11/5642 , G11C16/26 , G11C16/3427 , G11C2211/5648 , H01L27/1157 , H01L27/11582
摘要： A read operation for selected memory cell on a selected word line compensates for program disturb which is a nonlinear function of the data state of an adjacent memory cell on an adjacent word line. When a command to perform a read operation for the selected memory cell is received, a read operation is first performed on the adjacent memory cell to determine its data state, or to classify the adjacent memory cell into a threshold voltage range which includes one or more data states, or a portion of a data state. The selected memory cell is then read using a baseline control gate voltage which does not provide compensation, and one or more elevated control gate voltages which provide compensation, to distinguish between two adjacent data states. An optimal sensing result is selected based on the data state or threshold voltage range of the adjacent memory cell.
摘要翻译：对所选择的字线上的所选存储单元的读操作补偿作为相邻字线上相邻存储单元的数据状态的非线性函数的程序干扰。当接收到对所选择的存储单元执行读取操作的命令时，首先对相邻的存储器单元执行读取操作以确定其数据状态，或将相邻的存储器单元分类为包括一个或多个数据状态或数据状态的一部分。然后使用不提供补偿的基线控制栅极电压以及提供补偿的一个或多个升高的控制栅极电压来读取所选择的存储器单元，以区分两个相邻的数据状态。基于相邻存储单元的数据状态或阈值电压范围来选择最佳感测结果。

5. 发明申请

WO2016057202A1 PROGRAMMING OF DRAIN SIDE WORD LINE TO REDUCE PROGRAM DISTURB AND CHARGE LOSS 审中-公开
标题翻译：排水侧边线编程减少程序干扰和充电损失
公开(公告)号：WO2016057202A1
公开(公告)日：2016-04-14
申请号：PCT/US2015/051275
申请日：2015-09-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , DONG, Yingda , LU, Ching-Huang , ZHAO, Wei
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word line of the set. Pass voltages applied to the other word lines act as stress pulses which redistribute holes in the charge-trapping material of the memory cells of the other word lines to reduce short-term charge loss and downshifting of the threshold voltage. Additionally, one or more initial program voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of program disturb of erased state memory cells of the drain-side edge word line due to reduced channel boosting.
摘要翻译：提供了在编程集合的任何其他字线的存储器单元之前对一组字线集合的漏极边缘字线的存储器单元进行编程的技术。施加到其它字线的通过电压作为应力脉冲，其重新分配其它字线的存储单元的电荷捕获材料中的空穴，以减少阈值电压的短期电荷损耗和降档。此外，用于漏极侧边缘字线的一个或多个初始编程电压相对较低并且还用作应力脉冲。漏极侧边缘字线的存储单元被编程到比其它字线的存储单元窄的Vth窗口。这由于减少的信道增强而补偿了漏极侧边缘字线的擦除状态存储单元的编程干扰的较高水平。

6. 发明申请

WO2016093935A1 METHOD TO RECOVER CYCLING DAMAGE AND IMPROVE LONG TERM DATA RETENTION 审中-公开
标题翻译：恢复循环损伤并改善长期数据保留的方法
公开(公告)号：WO2016093935A1
公开(公告)日：2016-06-16
申请号：PCT/US2015/054454
申请日：2015-10-07
申请人： SANDISK TECHNOLOGIES INC.
发明人： LU, Ching-Huang , ZHANG, Zhengyi , ZHAO, Wei , DONG, Yingda , CHEN, Jian
IPC分类号： G11C16/34
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/0483 , G11C16/32 , G11C16/3431 , G11C16/3459 , G11C16/349 , G11C16/3495
摘要： Techniques for reversing damage caused by program-erase cycles in charge-trapping memory to improve long term data retention. A recovery process improves the data retention of a block of memory cells by programming the memory cells to a relatively high threshold voltage and enforcing a time period of several minutes or hours in which the memory cells are inactive and remain at the relatively high Vth levels. Damage such as traps in the memory cells is essentially healed or annealed out during this inactive period. All of the memory cells can be healed at the same time and by relatively equal amounts. At the conclusion of the recovery process, the block is returned to a pool of available blocks. In one approach, an amount of recovery is measured and the period of inactivity is continued for an amount of time which is based on the amount of recovery
摘要翻译：用于在电荷捕获存储器中逆转由编程擦除周期引起的损坏以改善长期数据保持的技术。恢复过程通过将存储器单元编程到相对较高的阈值电压并且执行存储器单元不活动并保持在相对高的Vth电平的几分钟或数小时的时间段来改善存储器单元块的数据保持。在这个不活跃的时期，诸如记忆单元中的陷阱的损伤基本上被愈合或退火。所有的记忆细胞可以同时和相对相等的量治愈。在恢复过程结束时，块将返回到可用块池。在一种方法中，测量恢复量，并且不活动的持续时间持续一段时间量，其基于恢复量

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