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1. 发明申请

WO2016025191A1 THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF 审中-公开
标题翻译：三维NAND STRING存储器件及其制造方法
公开(公告)号：WO2016025191A1
公开(公告)日：2016-02-18
申请号：PCT/US2015/043072
申请日：2015-07-31
申请人： SANDISK TECHNOLOGIES INC.
发明人： LEE, Yao-Sheng , PACHAMUTHU, Jayavel , MAKALA, Raghuveer S. , MATAMIS, George , ALSMEIER, Johann , CHIEN, Henry
IPC分类号： H01L27/115
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L27/11524 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11582 , H01L29/0649 , H01L29/1033 , H01L29/42324 , H01L29/4234 , H01L29/513 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/792
摘要： A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching the stack to form a front side opening, partially removing the second material layers through the front side opening to form front side recesses, forming a first blocking dielectric in the front side recesses, forming charge storage regions over the first blocking dielectric in the front side recesses, forming a tunnel dielectric layer and a semiconductor channel over the charge storage regions in the front side opening, etching the stack to form a back side opening, removing the second material layers through the back side opening to form back side recesses using the first blocking dielectric as an etch stop, forming a second blocking dielectric in the back side recesses, and forming control gates over the second blocking dielectric in the back side recesses.
摘要翻译：制造单片三维NAND串的方法包括在衬底上形成交替的第一和第二材料层的叠层，蚀刻叠层以形成前侧开口，通过前侧开口部分去除第二材料层以形成正面凹部，在前侧凹部中形成第一阻挡电介质，在前侧凹部中的第一阻挡电介质的上方形成电荷存储区域，在前侧开口的电荷存储区域上形成隧道电介质层和半导体沟道，蚀刻堆叠以形成背侧开口，通过背侧开口移除第二材料层，以形成使用第一阻挡电介质作为蚀刻停止件的后侧凹槽，在后侧凹部中形成第二阻挡电介质，并在在后侧凹槽中的第二阻挡电介质。

2. 发明申请

WO2013012682A2 COPPER INTERCONNECTS SEPARATED BY AIR GAPS AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：通过空气隙分离的铜互连件及其制造方法
公开(公告)号：WO2013012682A2
公开(公告)日：2013-01-24
申请号：PCT/US2012/046490
申请日：2012-07-12
申请人： SANDISK TECHNOLOGIES INC. , PURAYATH, Vinod R. , KAI, James K. , PACHAMUTHU, Jayavel , LIANG, Jarrett Jun , MATAMIS, George , HONMA, Ryoichi
发明人： PURAYATH, Vinod R. , KAI, James K. , PACHAMUTHU, Jayavel , LIANG, Jarrett Jun , MATAMIS, George , HONMA, Ryoichi
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/7682 , H01L21/76834 , H01L21/76849 , H01L21/76882 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.
摘要翻译：包括多个铜互连的半导体器件。多个铜互连的至少第一部分在顶面中具有弯月面。所述半导体器件还包括多个气隙，其中所述多个气隙中的每个气隙位于所述多个位线的至少所述第一部分的相邻对之间。

3. 发明申请

WO2016064509A1 THREE DIMENSIONAL NAND DEVICE CONTAINING FLUORINE DOPED LAYER AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：含有荧光体层的三维NAND器件及其制造方法
公开(公告)号：WO2016064509A1
公开(公告)日：2016-04-28
申请号：PCT/US2015/051261
申请日：2015-09-21
申请人： SANDISK TECHNOLOGIES, INC.
发明人： RABKIN, Peter , PACHAMUTHU, Jayavel , ALSMEIER, Johann
IPC分类号： H01L27/115 , H01L21/28 , H01L21/02
CPC分类号： H01L27/11582 , H01L21/02131 , H01L21/0214 , H01L21/0217 , H01L21/02178 , H01L21/02274 , H01L21/0228 , H01L21/02321 , H01L21/02326 , H01L21/02337 , H01L21/0234 , H01L21/28282 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/167 , H01L29/42364 , H01L29/51 , H01L29/518 , H01L29/7883
摘要： Disclosed is a monolithic three dimensional NAND string and a method for forming the same, comprising forming a stack of alternating layers of a first material (3) and a second material (19) different from the first material over a substrate, forming an at least one front side opening in the stack and forming at least a portion of a memory film (13) in the at least one front side opening. The method also includes forming a semiconductor channel (1) in the at least one front side opening and doping at least one of the memory film and the semiconductor channel with fluorine in-situ during deposition or by annealing in a fluorine containing atmosphere.
摘要翻译：公开了一种单片三维NAND串及其形成方法，包括在衬底上形成与第一材料不同的第一材料（3）和第二材料（19）的交替层的堆叠，至少形成在所述堆叠中的一个前侧开口，并且形成所述至少一个前侧开口中的记忆膜（13）的至少一部分。该方法还包括在所述至少一个前侧开口中形成半导体沟道（1），并且在沉积期间或通过在含氟气氛中退火而在存储膜和半导体沟道中的至少一个上原位掺杂。

4. 发明申请

WO2016022319A2 PROTECTIVE MATERIAL TO PREVENT SHORT CIRCUITS IN THREE-DIMENSIONAL MEMORY DEVICE 审中-公开
标题翻译：防止三维存储设备中的短路的保护材料
公开(公告)号：WO2016022319A2
公开(公告)日：2016-02-11
申请号：PCT/US2015/042302
申请日：2015-07-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , PACHAMUTHU, Jayavel , DONG, Yingda , ZHAO, Wei
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , G01R31/025 , G11C16/0483 , G11C29/025 , H01L21/32136 , H01L21/76224 , H01L27/0255 , H01L27/0288 , H01L27/0629 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L28/20 , H01L28/40 , H01L29/16 , H01L29/42328 , H01L29/42344 , H01L29/6609 , H01L29/861
摘要： In a three-dimensional stacked non-volatile memory device, a short circuit is prevented in a select gate layer by providing a protective material such as a diode, capacitor, linear resistor or varistor between select gate lines and a remaining portion of the select gate layer. Charges which are accumulated in the select gate lines due to plasma etching are therefore prevented from discharging through the remaining portion in a short circuit path when the select gate lines are driven. The protective material can comprise a p-n diode, an n-i-n or p-i-p resistor, a thin oxide layer between doped polysilicon layers in a capacitor, or a variable-resistance material such as ZnO2 between oxide layers in a varistor.
摘要翻译：在三维堆叠式非易失性存储器件中，通过在选择栅极线之间提供诸如二极管，电容器，线性电阻器或变阻器之类的保护材料来防止选择栅极层中的短路和选择栅极层的剩余部分。因此，当选择栅极线被驱动时，由于等离子体蚀刻而累积在选择栅极线中的电荷被阻止通过短路路径中的剩余部分放电。保护材料可以包括p-n二极管，n-i-n或p-i-p电阻器，电容器中掺杂多晶硅层之间的薄氧化物层，或变阻器中氧化物层之间的可变电阻材料，例如ZnO2。

5. 发明申请

WO2015002867A1 METHOD OF MAKING A THREE-DIMENSIONAL MEMORY ARRAY WITH ETCH STOP 审中-公开
标题翻译：使用蚀刻停止制作三维存储阵列的方法
公开(公告)号：WO2015002867A1
公开(公告)日：2015-01-08
申请号：PCT/US2014/044833
申请日：2014-06-30
申请人： SANDISK TECHNOLOGIES, INC.
发明人： MAKALA, Raghuveer S. , ALSMEIER, Johann , LEE, Yao-Sheng , TERAHARA, Masanori , WATATANI, Hirofumi , PACHAMUTHU, Jayavel
IPC分类号： H01L21/822 , H01L27/06 , H01L27/115
CPC分类号： H01L27/11582 , H01L21/8221 , H01L27/0688 , H01L27/1157
摘要： A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成牺牲特征，通过具有蚀刻穿过材料的区域和在所述牺牲特征上具有蚀刻停止材料的蚀刻停止区域形成多个蚀刻，形成交替层在所述多个蚀刻通过区域和所述多个蚀刻停止区域之上的第一材料和第二材料，蚀刻所述堆叠以形成穿过所述堆叠并穿过所述蚀刻通过区域以暴露所述牺牲特征的多个开口，使得与叠层的第一和第二材料相比，优先蚀刻蚀刻材料，通过多个开口去除牺牲特征并蚀刻叠层以形成直到或仅部分地穿过蚀刻停止区域的狭缝沟槽，使得与蚀刻停止材料相比，优先蚀刻叠层的第一和第二材料。

6. 发明申请

WO2016076955A1 THREE DIMENSIONAL NAND DEVICE HAVING REDUCED WAFER BOWING AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有减少波浪的三维NAND器件及其制造方法
公开(公告)号：WO2016076955A1
公开(公告)日：2016-05-19
申请号：PCT/US2015/052712
申请日：2015-09-28
申请人： SANDISK TECHNOLOGIES, INC.
发明人： BAENNINGER, Matthias , PACHAMUTHU, Jayavel , ALSMEIER, Johann
IPC分类号： H01L27/115 , H01L23/00
CPC分类号： H01L29/7846 , H01L23/562 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, and at least one trench extending substantially perpendicular to the major surface of the substrate. The trench is filled with at least a first trench material and a second trench material. The first trench material includes a material under a first magnitude of a first stress type, and the second trench material includes a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate.
摘要翻译：单片三维NAND串包括基本上平行于衬底的主表面延伸的多个控制栅极电极以及基本上垂直于衬底主表面延伸的至少一个沟槽。沟槽填充有至少第一沟槽材料和第二沟槽材料。第一沟槽材料包括第一应力类型的第一大小的材料，第二沟槽材料包括无应力的材料，与第一应力类型相反的第二应力类型或低于第一应力类型的第一应力类型的第二应力类型第一应力类型的第一大小，以抵消由于基板上的至少一个第一沟槽材料或多个控制栅电极施加的应力而导致的基板的翘曲。

7. 发明申请

WO2016064514A1 DEUTERIUM ANNEAL OF SEMICONDUCTOR CHANNELS IN A THREE-DIMENSIONAL MEMORY STRUCTURE 审中-公开
标题翻译：三维存储器结构中半导体通道的绝缘子
公开(公告)号：WO2016064514A1
公开(公告)日：2016-04-28
申请号：PCT/US2015/051484
申请日：2015-09-22
申请人： SANDISK TECHNOLOGIES, INC.
发明人： ZHAO, Wei , DONG, Yingda , CHOWDHURY, Murshed , PACHAMUTHU, Jayavel , ALSMEIER, Johann
IPC分类号： H01L27/115 , H01L21/30
CPC分类号： H01L27/11556 , H01L21/223 , H01L21/3003 , H01L21/324 , H01L27/11582 , H01L29/04 , H01L29/16
摘要： A monolithic three-dimensional memory structure includes a memory stack structure including a memory film and a semiconductor channel. Traps and/or defects within the semiconductor channel and/or at the semiconductor/dielectric material interface and/or inside dielectric materials can be passivated by an anneal in a deuterium-containing gas, which replaces hydrogen atoms within the semiconductor channel or passivate the dangling bonds/traps with deuterium atoms. The anneal may be performed immediately after formation of the semiconductor channel, before or after formation of a dielectric core or a drain region, after replacement of sacrificial material layers with conductive material layers, after dicing of a substrate into semiconductor chips, or at another suitable processing step.
摘要翻译：单片三维存储器结构包括存储器堆叠结构，其包括存储器膜和半导体通道。半导体通道内和/或半导体/电介质材料界面和/或内部电介质材料内的陷阱和/或缺陷可以通过在含氘气中进行退火来钝化，该气体取代了半导体通道内的氢原子或钝化了悬空具有氘原子的键/陷阱。在将衬底切割成半导体芯片之后，或者在另一个合适的方法中，在用导电材料层替换牺牲材料层之后，可以在形成半导体沟道之后，在形成介电芯或漏极区之前或之后执行退火处理步骤。

8. 发明申请

WO2016060787A1 THREE-DIMENSIONAL MEMORY STRUCTURE HAVING SELF-ALIGNED DRAIN REGIONS AND METHODS OF MAKING THEREOF 审中-公开
标题翻译：具有自对准排水区域的三维记忆结构及其制备方法
公开(公告)号：WO2016060787A1
公开(公告)日：2016-04-21
申请号：PCT/US2015/051175
申请日：2015-09-21
申请人： SANDISK TECHNOLOGIES, INC.
发明人： PANG, Liang , PACHAMUTHU, Jayavel , DONG, Yingda
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/2236 , H01L21/76802 , H01L21/76877 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/41741 , H01L29/511 , H01L29/518 , H01L29/7827
摘要： A memory stack structure can be formed through a stack of an alternating plurality of first material layers (32) and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film (50) and a semiconductor channel layer (60). The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region (63).
摘要翻译：存储器堆叠结构可以通过交替的多个第一材料层（32）和第二材料层的堆叠形成，并且通过具有与第一和第二材料层不同的组成的上覆临时材料层形成。存储器堆叠结构可以包括存储膜（50）和半导体沟道层（60）。上覆的临时材料层被选择性地移除到堆叠以形成横向凹部。存储膜的一部分在横向凹槽周围被去除，并且掺杂剂被横向引入到半导体沟道的上部，以形成自对准的漏极区（63）。

9. 发明申请

WO2016022320A1 BIAS TO DETECT AND PREVENT SHORT CIRCUITS IN THREE-DIMENSIONAL MEMORY DEVICE 审中-公开
标题翻译：检测和预防三维存储器件中的短路电路
公开(公告)号：WO2016022320A1
公开(公告)日：2016-02-11
申请号：PCT/US2015/042305
申请日：2015-07-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , PACHAMUTHU, Jayavel , DONG, Yingda , ZHAO, Wei
IPC分类号： G11C16/24 , G11C29/02
CPC分类号： G11C16/10 , G11C7/12 , G11C16/24 , G11C16/26 , G11C29/021 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , H01L21/8221
摘要： In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit occurs when charges accumulated in select gate lines due to plasma etching, discharge through a the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates the bias exceeds a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit.
摘要翻译：在三维堆叠式非易失性存储器件中，检测并防止了选择栅极层中的短路。当选择栅极线由于等离子体蚀刻而累积的电荷在选择栅极线被驱动时通过选择栅极层在短路路径中放电而发生短路。为了检测短路，在测试阶段期间，当测量电流时，向剩余部分施加增加的偏差。高于阈值的电流增加表示偏压超过短路路径的击穿电压。此时的偏差值被记录为最佳偏差。在涉及选择栅晶体管或存储单元（例如编程，擦除或读取）的后续操作期间，当驱动选择栅极线以防止电流流过短路时施加最佳偏压。

10. 发明申请

WO2015195405A1 A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE HAVING A SILICIDE SOURCE LINE AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有硅源线的三维非易失性存储器件及其制造方法
公开(公告)号：WO2015195405A1
公开(公告)日：2015-12-23
申请号：PCT/US2015/034832
申请日：2015-06-09
申请人： SANDISK TECHNOLOGIES, INC.
发明人： PACHAMUTHU, Jayavel , DONG, Yingda , ALSMEIER, Johann
IPC分类号： H01L27/115 , H01L29/66
CPC分类号： H01L27/11582 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/76886 , H01L21/76889 , H01L23/528 , H01L23/53209 , H01L23/53219 , H01L23/53233 , H01L23/53261 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A memory device and a method of making a memory device that includes a stack of alternating layers of a first material and a second material different from the first material over a substrate, where the layers of the second material form a plurality of conductive control gate electrodes. A plurality of NAND memory strings extend through the stack, where each NAND memory string includes a semiconductor channel which contains at least a first portion which extends substantially perpendicular to a major surface of the substrate and at least one memory film located between the semiconductor channel and the plurality of conductive control gate electrodes. A source line including a metal silicide material extends through the stack.
摘要翻译：一种存储器件和制造存储器件的方法，所述存储器件包括在衬底上的第一材料和不同于第一材料的第二材料的交替层的叠层，其中第二材料的层形成多个导电控制栅电极。多个NAND存储器串延伸通过堆栈，其中每个NAND存储器串包括半导体通道，该半导体通道至少包含基本上垂直于衬底主表面延伸的第一部分和位于半导体通道和多个导电控制栅电极。包括金属硅化物材料的源极线延伸穿过堆叠。

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