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1. 发明申请

WO2008137687A1 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 审中-公开
标题翻译：使用通道隔离开关来促进非易失性存储
公开(公告)号：WO2008137687A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062432
申请日：2008-05-02
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

2. 发明申请

WO2009143435A1 ENHANCED BIT-LINE PRE-CHARGE SCHEME FOR INCREASING CHANNEL BOOSTING IN NON-VOLATILE STORAGE 审中-公开
标题翻译：增强非易失性存储器中的通道增强的双线预先计费方案
公开(公告)号：WO2009143435A1
公开(公告)日：2009-11-26
申请号：PCT/US2009/044999
申请日：2009-05-22
申请人： SANDISK CORPORATION , DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/10 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/32 , G11C16/3418 , G11C16/3427
摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.
摘要翻译：在非易失性存储器中改善通道增强以减少程序干扰。预充电模块电压源用于在编程操作期间预充电位线。预充电模块电压源通过位线耦合到衬底通道以升高通道。通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

3. 发明申请

WO2008083221A2 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY USING DIFFERENT PRE-CHARGE ENABLE VOLTAGES 审中-公开
标题翻译：通过使用不同的预充电使能电压来编程具有减少程序故障的非易失性存储器
公开(公告)号：WO2008083221A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/088947
申请日：2007-12-27
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana
发明人： HEMINK, Gerrit, Jan , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana
IPC分类号： G11C16/12
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5628 , G11C16/3418
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.
摘要翻译：未编程的非易失性存储元件组在编程期间升压，以减少或消除连接到所选字线的目标但未选定的存储单元的编程干扰。在将编程电压施加到所选字线并提升未选定组之前，未选定组被预充电以通过为未选定组提供更大的提升电位来进一步减少或消除编程干扰。在预充电期间，对于特定的非易失性存储元件，以不同的电压提供一个或多个预充电使能信号。

4. 发明申请

WO2008083214A1 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY REMOVING PRE-CHARG DEPENDENCY ON WORD LINE DATA 审中-公开
标题翻译：通过在字线数据上删除预先确定的程序来编程减少程序干扰的非易失性存储器
公开(公告)号：WO2008083214A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088931
申请日：2007-12-27
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana , HEMINK, Gerrit, Jan
IPC分类号： G11C16/04 , G11C16/12 , G11C11/56
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.
摘要翻译：在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。在预充电期间，对于可能已经经过部分编程的某些存储器单元，在较高电压下提供一个或多个预充电使能信号。

5. 发明申请

WO2011133404A1 PROGRAMMING NON-VOLATILE STORAGE INCLUDNG REDUCING IMPACT FROM OTHER MEMORY CELLS 审中-公开
标题翻译：编程非易失性存储包括减少其他记忆细胞的影响
公开(公告)号：WO2011133404A1
公开(公告)日：2011-10-27
申请号：PCT/US2011/032575
申请日：2011-04-14
申请人： SANDISK CORPORATION , DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
发明人： DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/3459 , G11C2211/5621 , G11C2211/5622
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，使用随时间增加的编程信号将第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，使用已经响应于第一触发而被大幅度降低的编程信号，将第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起编程，响应于第二触发而使编程信号升高。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

6. 发明申请

WO2013126109A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：WO2013126109A1
公开(公告)日：2013-08-29
申请号：PCT/US2012/066909
申请日：2012-11-28
申请人： SANDISK TECHNOLOGIES, INC. , OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
发明人： OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
IPC分类号： G11C29/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

7. 发明申请

WO2011127195A1 SAW-SHAPED MULTI-PULSE PROGRAMMING FOR PROGRAM NOISE REDUCTION IN MEMORY 审中-公开
标题翻译：存储器中程序噪声减少的SAW形状多脉冲编程
公开(公告)号：WO2011127195A1
公开(公告)日：2011-10-13
申请号：PCT/US2011/031452
申请日：2011-04-06
申请人： SANDISK CORPORATION , DONG, Yingda , FONG, Yupin, K. , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , FONG, Yupin, K. , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/10
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C2211/5621 , G11C2211/5622
摘要： In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.
摘要翻译：在存储器系统中，编程波形通过使用具有锯齿形状的多个相邻子脉冲的集合来减少编程噪声。在一组中，初始子脉冲从初始电平（例如0V）升高到峰值电平，然后降至高于初始电平的中间电平。集合的一个或多个后续子脉冲可以从中间电平升高到峰值电平，然后降低到中间电平。集合的最后一个子脉冲可以从中间电平升高到峰值电平，然后降低到初始电平。在子脉冲组之后执行验证操作。每组的子脉冲数可以在连续的集合中减小，直到在编程操作结束时施加孤立脉冲。

8. 发明申请

WO2011022386A1 SELECTIVE MEMORY CELL PROGRAM AND ERASE 审中-公开
标题翻译：选择性记忆细胞程序和删除
公开(公告)号：WO2011022386A1
公开(公告)日：2011-02-24
申请号：PCT/US2010/045744
申请日：2010-08-17
申请人： SANDISK CORPORATION , DONG, Yingda , KUO, Tien-chien , HEMINK, Gerrit Jan
发明人： DONG, Yingda , KUO, Tien-chien , HEMINK, Gerrit Jan
IPC分类号： G11C16/16 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3418 , G11C2211/5641
摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.
摘要翻译：本文公开了用于编程存储器阵列以实现高编程/擦除周期耐久性的技术。在某些方面，只有选择的字线（WL）被编程，其他WL保持未编程。作为示例，只有偶数字线被编程，剩余的未编程的奇数WL。在所有偶数字线被编程并且数据块要用新数据编程之后，块被擦除。之后，只有奇数字线被编程。数据可以被传送到在擦除之前存储多个存储单元的位的块。在一个方面，数据以棋盘格式编程，其中编程了一些存储器单元，而其他存储器单元未被编程。之后，在擦除数据之后，棋盘格图案的以前未编程的部分被编程为剩余的单元未编程。

9. 发明申请

WO2011005401A2 REDUCED PROGRAMMING PULSE WIDTH FOR ENHANCED CHANNEL BOOSTING IN NON-VOLATILE STORAGE 审中-公开
标题翻译：减少编程脉冲宽度以增强非易失性存储器的通道提升
公开(公告)号：WO2011005401A2
公开(公告)日：2011-01-13
申请号：PCT/US2010/037839
申请日：2010-06-08
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W.
发明人： DONG, Yingda , LUTZE, Jeffrey, W.
IPC分类号： G11C16/10
CPC分类号： G11C16/10
摘要： Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter duration, partway through the programming operation. A switchover point can be based on temperature, selected word line position and/or tracking of storage elements to a trigger state. The switchover point occurs sooner for higher temperatures, and for drain side word lines. The trigger state can be selected based on temperature. A portion of storage elements which are required to reach the trigger state to trigger a switchover can also be set a function of temperature. Programming pulses of a shorter duration improve channel boosting for inhibited storage elements, thereby reducing program disturb for these storage elements.
摘要翻译：在编程操作期间，通过从使用较长持续时间的编程脉冲切换到在编程操作中途的较短持续时间的编程脉冲的切换，在非易失性存储系统中减少了编程干扰。切换点可以基于温度，所选字线位置和/或将存储元件跟踪到触发状态。对于较高的温度以及对于漏极侧字线，切换点更快发生。触发状态可以根据温度进行选择。达到触发状态以触发切换所需的存储元件的一部分也可以被设置为温度的函数。持续时间较短的编程脉冲可改善受抑制存储元件的通道升压，从而减少这些存储元件的编程干扰。

10. 发明申请

WO2010017013A1 COMPENSATING FOR COUPLING DURING READ OPERATIONS IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中读取操作期间的耦合补偿
公开(公告)号：WO2010017013A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/050974
申请日：2009-07-17
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
IPC分类号： G11C11/56 , G11C16/24
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3418
摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.
摘要翻译：通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压字线。当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据相邻存储元件。

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