专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2009143435A1 ENHANCED BIT-LINE PRE-CHARGE SCHEME FOR INCREASING CHANNEL BOOSTING IN NON-VOLATILE STORAGE 审中-公开
标题翻译：增强非易失性存储器中的通道增强的双线预先计费方案
公开(公告)号：WO2009143435A1
公开(公告)日：2009-11-26
申请号：PCT/US2009/044999
申请日：2009-05-22
申请人： SANDISK CORPORATION , DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , MUI, Man, L. , LUTZE, Jeffrey, W. , SATO, Shinji , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/10 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/32 , G11C16/3418 , G11C16/3427
摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.
摘要翻译：在非易失性存储器中改善通道增强以减少程序干扰。预充电模块电压源用于在编程操作期间预充电位线。预充电模块电压源通过位线耦合到衬底通道以升高通道。通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

2. 发明申请

WO2008137687A1 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 审中-公开
标题翻译：使用通道隔离开关来促进非易失性存储
公开(公告)号：WO2008137687A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062432
申请日：2008-05-02
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

3. 发明申请

WO2008083221A2 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY USING DIFFERENT PRE-CHARGE ENABLE VOLTAGES 审中-公开
标题翻译：通过使用不同的预充电使能电压来编程具有减少程序故障的非易失性存储器
公开(公告)号：WO2008083221A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/088947
申请日：2007-12-27
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana
发明人： HEMINK, Gerrit, Jan , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana
IPC分类号： G11C16/12
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5628 , G11C16/3418
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.
摘要翻译：未编程的非易失性存储元件组在编程期间升压，以减少或消除连接到所选字线的目标但未选定的存储单元的编程干扰。在将编程电压施加到所选字线并提升未选定组之前，未选定组被预充电以通过为未选定组提供更大的提升电位来进一步减少或消除编程干扰。在预充电期间，对于特定的非易失性存储元件，以不同的电压提供一个或多个预充电使能信号。

4. 发明申请

WO2008083214A1 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY REMOVING PRE-CHARG DEPENDENCY ON WORD LINE DATA 审中-公开
标题翻译：通过在字线数据上删除预先确定的程序来编程减少程序干扰的非易失性存储器
公开(公告)号：WO2008083214A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088931
申请日：2007-12-27
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana , HEMINK, Gerrit, Jan
IPC分类号： G11C16/04 , G11C16/12 , G11C11/56
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.
摘要翻译：在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。在预充电期间，对于可能已经经过部分编程的某些存储器单元，在较高电压下提供一个或多个预充电使能信号。

5. 发明申请

WO2011127195A1 SAW-SHAPED MULTI-PULSE PROGRAMMING FOR PROGRAM NOISE REDUCTION IN MEMORY 审中-公开
标题翻译：存储器中程序噪声减少的SAW形状多脉冲编程
公开(公告)号：WO2011127195A1
公开(公告)日：2011-10-13
申请号：PCT/US2011/031452
申请日：2011-04-06
申请人： SANDISK CORPORATION , DONG, Yingda , FONG, Yupin, K. , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , FONG, Yupin, K. , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/10
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C2211/5621 , G11C2211/5622
摘要： In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.
摘要翻译：在存储器系统中，编程波形通过使用具有锯齿形状的多个相邻子脉冲的集合来减少编程噪声。在一组中，初始子脉冲从初始电平（例如0V）升高到峰值电平，然后降至高于初始电平的中间电平。集合的一个或多个后续子脉冲可以从中间电平升高到峰值电平，然后降低到中间电平。集合的最后一个子脉冲可以从中间电平升高到峰值电平，然后降低到初始电平。在子脉冲组之后执行验证操作。每组的子脉冲数可以在连续的集合中减小，直到在编程操作结束时施加孤立脉冲。

6. 发明申请

WO2006036453A3 NON-VOLATILE NAND MEMORY WITH ASYMMETRICAL DOPING PROFILE 审中-公开
公开(公告)号：WO2006036453A3
公开(公告)日：2006-04-06
申请号：PCT/US2005/031279
申请日：2005-08-26
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , SATO, Shinji
发明人： HEMINK, Gerrit, Jan , SATO, Shinji
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336 , H01L29/788 , G11C16/04
摘要： Stacked gate structures (408A,480B,480C) for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantation’s are performed at a 5-second implantation angle to areas between the stacked gate structures. The drain implantations (498) create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations (496) create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures. A B-halo (494) can be formed as well.

7. 发明申请

WO2011103013A1 NON-VOLATILE STORAGE WITH TEMPERATURE COMPENSATION BASED ON NEIGHBOR STATE INFORMATION 审中-公开
标题翻译：基于邻国状态信息的温度补偿非挥发性储存
公开(公告)号：WO2011103013A1
公开(公告)日：2011-08-25
申请号：PCT/US2011/024287
申请日：2011-02-10
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , SATO, Shinji
发明人： HEMINK, Gerrit, Jan , SATO, Shinji
IPC分类号： G11C11/56
CPC分类号： G11C16/26 , G11C7/04 , G11C11/5642
摘要： Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target memory cells, the system senses the current temperature and determines the differences in temperature between the current temperature and the temperature at the time the data was programmed. If the difference in temperature is greater than a threshold, then the process of reading the data includes providing temperature compensation based on temperature information and neighbor state information. In one alternative, the decision to provide the temperature compensation can be triggered by conditions other than a temperature differential.
摘要翻译：数据被编程到一组目标存储器单元中并从其读取。读取数据时，提供温度补偿。温度补偿基于温度信息和一个或多个相邻存储单元的状态。在一个实施例中，当从目标存储器单元的集合读取数据时，系统感测当前温度并确定当前温度与数据编程时的温度之间的温度差。如果温度差大于阈值，则读取数据的过程包括基于温度信息和邻近状态信息提供温度补偿。在一个替代方案中，提供温度补偿的决定可以由温差以外的条件触发。

8. 发明申请

WO2013126109A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：WO2013126109A1
公开(公告)日：2013-08-29
申请号：PCT/US2012/066909
申请日：2012-11-28
申请人： SANDISK TECHNOLOGIES, INC. , OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
发明人： OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
IPC分类号： G11C29/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

9. 发明申请

WO2013147937A1 SELECTED WORD LINE DEPENDENT SELECT GAME VOLTAGE DURING PROGRAM 审中-公开
标题翻译：在程序期间选择的字线相关选择游戏电压
公开(公告)号：WO2013147937A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/066611
申请日：2012-11-27
申请人： SANDISK TECHNOLOGIES, INC. , LAI, Chun-hung , DUTTA, Deepanshu , SATO, Shinji , HEMINK, Gerrit, Jan
发明人： LAI, Chun-hung , DUTTA, Deepanshu , SATO, Shinji , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于选择用于编程的字线的位置，这可以减少或消除程序干扰。施加到NAND串的选择晶体管的栅极的电压可以取决于所选字线的位置。这可以是源极侧或漏极侧选择晶体管。这可能会阻止或减少由于DIBL而导致的程序干扰。这也可以防止或减少由于GIDL可能导致的程序干扰。当编程至少一些字线时，负偏压可以施加到源极侧选择晶体管的栅极。在一个实施例中，当编程逐渐增加的字线时，逐渐降低的电压用于漏极侧选择晶体管的栅极。

10. 发明申请

WO2011066234A1 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED NUMBER OF VERIFY OPERATIONS 审中-公开
标题翻译：编程非易失性存储器，具有减少的验证数量
公开(公告)号：WO2011066234A1
公开(公告)日：2011-06-03
申请号：PCT/US2010/057666
申请日：2010-11-22
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , HEMINK, Gerrit, Jan
发明人： DUTTA, Deepanshu , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3454 , G11C11/5628 , G11C16/3459 , G11C2211/5621
摘要： A method and non-volatile storage system are provided in which programming speed is increased by reducing the number of verify operations, while maintaining a narrow threshold voltage distribution. A programming scheme performs a verify operation at an offset level, before a verify level of a target data state is reached, such as to slow down programming. However, it is not necessary to perform verify operations at both the offset and target levels at all times. In a first programming phase, verify operations are performed for a given data state only at the target verify level. In a second programming phase, verify operations are performed for offset and target verify levels. In a third programming phase, verify operations are again performed only at the target verify level. Transitions between phases can be predetermined, based on programming pulse number, or adaptive.
摘要翻译：提供了一种方法和非易失性存储系统，其中通过减少验证操作的数量来增加编程速度，同时保持窄的阈值电压分布。在达到目标数据状态的验证级别之前，编程方案在偏移级别执行验证操作，例如减慢编程。但是，始终不必在偏移量和目标电平两者上执行验证操作。在第一个编程阶段，仅在目标验证级别对给定数据状态执行验证操作。在第二个编程阶段，对偏移和目标验证电平执行验证操作。在第三个编程阶段，仅在目标验证级别再次执行验证操作。相位之间的转换可以根据编程脉冲数或自适应来预先确定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式