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1. 发明申请

WO2011094419A1 MULTIBIT PROGRAMMING METHOD IN A NON-VOLATILE MEMORY ALLOWING A NUMBER OF DATA STATE - FAILS AND DATA RECOVERY METHOD IN CASE OF PROGRAMMING FAIL 审中-公开
标题翻译：非易失性存储器中的多编程方法允许数据状态 - 编程失败情况下的故障和数据恢复方法
公开(公告)号：WO2011094419A1
公开(公告)日：2011-08-04
申请号：PCT/US2011/022736
申请日：2011-01-27
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , YAN, Li
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , YAN, Li
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C16/3418 , G11C29/00 , G11C2211/5621 , G11C2211/5642
摘要： An error detection and data recovery operation for a non-volatile memory system. Even after a programming operation for a set of storage elements is successfully completed, the data of some storage elements may be corrupted. For example, erased state storage element may be disturbed by programming of other storage elements. To allow recovery of data in such situations, associated data latches can be configured to allow the erased state storage elements to be distinguished from other data states once programming is completed. Furthermore, a single read operation can be performed after programming is completed. Logical operations are performed using results from the read operation, and values in the data latches, to identify erased state storage elements which have strayed to another data state. If the number of errors exceeds a threshold, a full recovery operation is initiated in which read operations are performed for the remaining states.
摘要翻译：用于非易失性存储器系统的错误检测和数据恢复操作。即使在一组存储元件的编程操作成功完成之后，一些存储元件的数据也可能被破坏。例如，擦除状态存储元件可能受到其他存储元件的编程的干扰。为了允许在这种情况下恢复数据，相关联的数据锁存器可以被配置为允许擦除状态存储元件与编程完成之后的其它数据状态区分开。此外，可以在编程完成之后执行单个读取操作。使用读取操作的结果和数据锁存器中的值执行逻辑运算，以识别已经偏移到另一数据状态的擦除状态存储元件。如果错误数量超过阈值，则启动完全恢复操作，在其中执行剩余状态的读取操作。

2. 发明申请

WO2010051116A1 PAIR BIT LINE PROGRAMMING TO IMPROVE BOOST VOLTAGE CLAMPING 审中-公开
标题翻译：配对线编程，以提高升压钳位
公开(公告)号：WO2010051116A1
公开(公告)日：2010-05-06
申请号：PCT/US2009/058000
申请日：2009-09-23
申请人： SANDISK CORPORATION , LUTZE, Jeffrey, W. , DUTTA, Deepanshu
发明人： LUTZE, Jeffrey, W. , DUTTA, Deepanshu
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C2211/5621
摘要： A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.
摘要翻译：编程技术通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的编程干扰，这增加了禁止信道的钳位升压电位以避免编程干扰。一个方面将交替的相邻位线对组合成第一和第二组。双编程脉冲被施加到选定的字线。第一组位线在第一脉冲期间被编程，并且第二组位线在第二脉冲期间被编程。然后对所有位线执行验证操作。当特定位线被禁止时，其相邻位线中的至少一个也将被禁止，使得特定位线的通道将被充分提升。另一个方面分别编写每第三个位线。修改的布局允许使用奇偶校验感测电路来感测相邻的位线对。

3. 发明申请

WO2008073892A3 REDUCING PROGRAM DISTURB IN NON-VOLATILE STORAGE USING EARLY SOURCE-SIDE BOOSTING 审中-公开
标题翻译：使用早期源驱动减少非易失性存储中的程序干扰
公开(公告)号：WO2008073892A3
公开(公告)日：2008-07-31
申请号：PCT/US2007086981
申请日：2007-12-10
申请人： SANDISK CORP , DONG YINGDA , LUTZE JEFFREY W
发明人： DONG YINGDA , LUTZE JEFFREY W
IPC分类号： G11C16/10 , G11C16/04 , G11C16/12
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： Program disturb is reduced in non-volatile storage by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach, a first boost mode is used when the selected word line is a lower or intermediate word line. In the first boost mode, boosting of the source and drain side channels is initiated concurrently. A second boost mode is used when the selected word line is a higher word line. In the second boost mode, boosting of the source side channel occurs early relative to the boosting of the drain side channel. Either boost mode include an isolation voltage which tends to isolate the source and drain side channels from one another.
摘要翻译：在非易失性存储器中通过升高阵列中的未选择的NAND串来减少非易失性存储器中的编程干扰，使得在所选择的字的漏极侧之前，在所选字线的源极侧的源极通道被提升在漏极侧通道之前线。在一种方法中，当所选字线是较低或中间字线时，使用第一升压模式。在第一升压模式中，同时启动源极和漏极侧通道的升压。当所选字线是较高字线时，使用第二升压模式。在第二升压模式中，源侧通道的升压相对于漏极侧通道的升压而早期发生。升压模式包括易于将源极和漏极侧通道彼此隔离的隔离电压。

4. 发明申请

WO2008083221A2 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY USING DIFFERENT PRE-CHARGE ENABLE VOLTAGES 审中-公开
标题翻译：通过使用不同的预充电使能电压来编程具有减少程序故障的非易失性存储器
公开(公告)号：WO2008083221A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/088947
申请日：2007-12-27
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana
发明人： HEMINK, Gerrit, Jan , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana
IPC分类号： G11C16/12
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5628 , G11C16/3418
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.
摘要翻译：未编程的非易失性存储元件组在编程期间升压，以减少或消除连接到所选字线的目标但未选定的存储单元的编程干扰。在将编程电压施加到所选字线并提升未选定组之前，未选定组被预充电以通过为未选定组提供更大的提升电位来进一步减少或消除编程干扰。在预充电期间，对于特定的非易失性存储元件，以不同的电压提供一个或多个预充电使能信号。

5. 发明申请

WO2007076451A3 BODY EFFECT SENSING METHOD FOR NON-VOLATILE MEMORIES 审中-公开
公开(公告)号：WO2007076451A3
公开(公告)日：2007-07-05
申请号：PCT/US2006/062513
申请日：2006-12-21
申请人： SANDISK CORPORATION , MOKHLESI, Nima , LUTZE, Jeffrey W.
发明人： MOKHLESI, Nima , LUTZE, Jeffrey W.
IPC分类号： G11C11/56
摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

6. 发明申请

WO2005119696A1 ERASE VERIFICATION FOR NON-VOLATILE MEMORY BY TESTING THE CONDUCTION OF THE MEMORY ELEMENTS IN A FIRST AND A SECOND DIRECTION 审中-公开
标题翻译：通过测试第一和第二方向的记忆元素的导致来对非易失性存储器进行擦除验证
公开(公告)号：WO2005119696A1
公开(公告)日：2005-12-15
申请号：PCT/US2005/017862
申请日：2005-05-20
申请人： SANDISK CORPORATION , TRAN, Dat , PONNURU, Kiran , CHEN, Jian , LUTZE, Jeffrey, W. , WANG, Jun
发明人： TRAN, Dat , PONNURU, Kiran , CHEN, Jian , LUTZE, Jeffrey, W. , WANG, Jun
IPC分类号： G11C16/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a first (380) and a second (382) direction, defects in any transistors of the Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements in verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过测试第一（380）和第二（382）方向的串的充电或导通，根据各种实施例的系统和方法的任何晶体管中的缺陷可以提供非易失性半导体中的全面擦除验证和缺陷检测记忆。在一个实施例中，擦除使用多个测试条件验证的一组存储元件的结果，以更好地检测该组的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

7. 发明申请

WO2005091369A1 SELF ALIGNED NON-VOLATILE MEMORY CELLS AND PROCESSES FOR FABRICATION 审中-公开
标题翻译：自对准的非易失性记忆细胞和制备方法
公开(公告)号：WO2005091369A1
公开(公告)日：2005-09-29
申请号：PCT/US2005/007891
申请日：2005-03-09
申请人： SANDISK CORPORATION , LUTZE, Jeffrey W. , PHAM, Tuan , HIGASHITANI, Masaaki
发明人： LUTZE, Jeffrey W. , PHAM, Tuan , HIGASHITANI, Masaaki
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521
摘要： A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also provided. A first process forms floating gates by etching an upper portion of a polysilicon structure with masking elements in place to shape the floating gate. A second process etches recesses and protrusions in a polysilicon structure prior to etching the structure to form individual floating gates.
摘要翻译：非易失性存储器阵列具有耦合到浮动栅极的字线，浮动栅极具有适于提供增加的表面积的上部部分，从而提供增加的与字线的耦合。还提供了浮动门之间的屏蔽。第一工艺通过用掩蔽元件蚀刻多晶硅结构的上部来形成浮栅来形成浮栅，以形成浮栅。在蚀刻结构之前，第二工艺蚀刻多晶硅结构中的凹陷和突起以形成单独的浮动栅极。

8. 发明申请

WO2005073979A1 NON-VOLATILE MEMORY CELL USING HIGH-K MATERIAL AND INTER-GATE PROGRAMMING 审中-公开
标题翻译：使用高K材料和栅极编程的非易失性存储单元
公开(公告)号：WO2005073979A1
公开(公告)日：2005-08-11
申请号：PCT/US2005/000670
申请日：2005-01-10
申请人： SANDISK CORPORATION , MOKHLESI, Nima , LUTZE, Jeffrey, W.
发明人： MOKHLESI, Nima , LUTZE, Jeffrey, W.
IPC分类号： G11C16/04
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.
摘要翻译：非易失性存储器件在源极/漏极区域之间具有沟道区域，浮置栅极，控制栅极，沟道区域和浮置栅极之间的第一介电区域以及浮置栅极和控制栅极之间的第二介电区域。第一电介质区域包括高K材料。通过经由第二电介质区域在浮动栅极和控制栅极之间传送电荷来对非易失性存储器件进行编程和/或擦除。

9. 发明申请

WO2010017013A1 COMPENSATING FOR COUPLING DURING READ OPERATIONS IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中读取操作期间的耦合补偿
公开(公告)号：WO2010017013A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/050974
申请日：2009-07-17
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
IPC分类号： G11C11/56 , G11C16/24
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3418
摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.
摘要翻译：通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压字线。当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据相邻存储元件。

10. 发明申请

WO2008036484A3 NONVOLATILE MEMORY WITH REDUCED COUPLING BETWEEN FLOATING GATES 审中-公开
标题翻译：浮动门之间具有减少耦合的非易失性存储器
公开(公告)号：WO2008036484A3
公开(公告)日：2008-08-07
申请号：PCT/US2007076163
申请日：2007-08-17
申请人： SANDISK CORP , CHIEN HENRY , MATAMIS GEORGE , PHAM TUAN , HIGASHITANI MASAAKI , HORIUCHI HIDETAKA , LUTZE JEFFREY W , MOKHLESI NIMA , FONG YUPIN KAWING
发明人： CHIEN HENRY , MATAMIS GEORGE , PHAM TUAN , HIGASHITANI MASAAKI , HORIUCHI HIDETAKA , LUTZE JEFFREY W , MOKHLESI NIMA , FONG YUPIN KAWING
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
摘要翻译：非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。相邻的串由浅沟槽隔离结构隔离。具有倒T形浮置栅极的阵列可以以自对准的方式形成。

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