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1. 发明申请

WO2009006275A1 NON-VOLATILE STORAGE WITH SOURCE BIAS ALL BIT LINE SENSING 审中-公开
标题翻译：非挥发性存储与源偏移所有位线感测
公开(公告)号：WO2009006275A1
公开(公告)日：2009-01-08
申请号：PCT/US2008/068525
申请日：2008-06-27
申请人： SANDISK CORPORATION , LEE, Seungpil , NGUYEN, Hao Thai , MUI, Man Lung
发明人： LEE, Seungpil , NGUYEN, Hao Thai , MUI, Man Lung
IPC分类号： G11C16/26 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C2211/565
摘要： A NAND string in which bit line-to-bit line noise is discharged prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.
摘要翻译：在读取NAND串中选定的非易失性存储元件的编程条件之前，其中位线对位线噪声被放电的NAND串。施加源电压，其提高导电NAND串中的电压。电压升高导致噪声与相邻NAND串的电容耦合。电流下拉器件用于在执行感测之前对每个NAND串进行放电。在每个NAND串被连接到放电路径达预定时间量之后，NAND串的位线被耦合到电压感测组件，用于基于位线的电位感测所选择的非易失性存储元件的编程状态。所选择的非易失性存储元件可具有负阈值电压。此外，与所选择的非易失性存储元件相关联的字线可以被设置为接地。

2. 发明申请

WO2008121535A1 NON-VOLATILE MEMORY AND METHOD FOR COMPENSATION FOR VOLTAGE DROPS ALONG A WORD LINE 审中-公开
标题翻译：非挥发性记忆和方法，用于补偿字线上的电压降
公开(公告)号：WO2008121535A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/056975
申请日：2008-03-14
申请人： SANDISK CORPORATION , SEKAR, Deepak Chandra , MUI, Man Lung , MOKHLESI, Nima
发明人： SEKAR, Deepak Chandra , MUI, Man Lung , MOKHLESI, Nima
IPC分类号： G11C16/12 , G11C16/04 , G11C11/56
CPC分类号： G11C16/12 , G11C7/18 , G11C8/14 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/30
摘要： Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter.
摘要翻译：由跨越存储器平面的字线的时间常数变化引起的编程效能的变化通过调整整个平面上的位线电压来修正编程速率来补偿。以这种方式，在编程耦合到字线的一组存储器单元的编程期间，编程功效的变化显着降低。这将允许对存储器单元组进行编程的均匀优化，并且减少编程存储器单元组所需的编程脉冲数，从而提高性能。在一个实施例中，在编程期间，更靠近字线电压源的存储器平面的前半部分中的位线被第一电压移位器设置为第一电压，并且存储器平面的后半部分中的位线进一步从第二电压转换器将字线电压源设定为第二电压。

3. 发明申请

WO2009146057A1 HIGH SPEED SENSE AMPLIFIER ARRAY AND METHOD FOR NONVOLATILE MEMORY 审中-公开
标题翻译：高速感测放大器阵列和非易失性存储器的方法
公开(公告)号：WO2009146057A1
公开(公告)日：2009-12-03
申请号：PCT/US2009/039082
申请日：2009-04-01
申请人： SANDISK CORPORATION , NGUYEN, Hao, Thai , MUI, Man, Lung , LEE, Seungpil , ZHANG, Fanglin , WANG, Chi-Ming
发明人： NGUYEN, Hao, Thai , MUI, Man, Lung , LEE, Seungpil , ZHANG, Fanglin , WANG, Chi-Ming
IPC分类号： G11C16/26 , G11C11/56
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
摘要翻译：提供用于感测并联感测的一组非易失性存储器单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。预充电电路耦合到用于将节点充电到初始电压的节点。中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

4. 发明申请

WO2009126499A1 SENSING IN NON-VOLATILE STORAGE USING PULLDOWN TO REGULATED SOURCE VOLTAGE TO REMOVE SYSTEM NOISE 审中-公开
标题翻译：使用推挽方式将非挥发性储存感知到调节源电压以移除系统噪声
公开(公告)号：WO2009126499A1
公开(公告)日：2009-10-15
申请号：PCT/US2009/039211
申请日：2009-04-01
申请人： SANDISK CORPORATION , NGUYEN, Hao Thai , MUI, Man Lung , LEE, Seungpil , WANG, Chi-Ming
发明人： NGUYEN, Hao Thai , MUI, Man Lung , LEE, Seungpil , WANG, Chi-Ming
IPC分类号： G11C16/24 , G11C11/56
CPC分类号： G11C16/24 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3427 , G11C16/3454
摘要： A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common source line. When a selected storage element of a NAND string has been programmed to its intended state, the bit line is locked out during subsequent verify operations which occur for other NAND strings which are not yet locked out. The pull down device is coupled to each bit line and to the common source line, whose voltage is regulated at a positive DC level, to prevent coupling of system power bus (Vss) noise from the locked out bit lines to the not yet locked out bit lines.
摘要翻译：下拉电路在诸如在编程期间发生的验证操作的感测操作期间将位线电压拉到非易失性存储设备中的稳压源电压。存储设备可以包括具有相关联的位线和感测组件的NAND串，以及公共源线。当NAND串的所选择的存储元件已被编程到其预期状态时，在对尚未被锁定的其它NAND串发生的后续验证操作期间，位线被锁定。下拉装置耦合到每个位线和公共源极线，其电压被调节为正的直流电平，以防止将系统电源总线（Vss）噪声从锁定的位线耦合到尚未锁定位线。

5. 发明申请

WO2013126109A1 TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储的验证操作期间基于温度的补偿
公开(公告)号：WO2013126109A1
公开(公告)日：2013-08-29
申请号：PCT/US2012/066909
申请日：2012-11-28
申请人： SANDISK TECHNOLOGIES, INC. , OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
发明人： OOWADA, Ken , DONG, Yingda , HEMINK, Gerrit, Jan , MUI, Man, Lung , NGUYEN, Hao , LEE, Seungpil , PARK, Jong , ZHANG, Fanglin
IPC分类号： G11C29/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

6. 发明申请

WO2010077528A1 REGULATION OF RECOVERY RATES IN CHARGE PUMPS 审中-公开
标题翻译：充电泵中恢复率的调节
公开(公告)号：WO2010077528A1
公开(公告)日：2010-07-08
申请号：PCT/US2009/066268
申请日：2009-12-01
申请人： SANDISK CORPORATION , MUI, Man Lung , LEE, Seungpil , NGUYEN, Hao Thai
发明人： MUI, Man Lung , LEE, Seungpil , NGUYEN, Hao Thai
IPC分类号： H02M3/07 , G11C5/14 , G11C16/30
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30
摘要： A method is presented of setting a frequency of a clock for a charge pump system including the clock and a charge pump. This includes setting an initial value for the frequency of the clock and, while operating the charge pump system using the clock running at the initial frequency value, determining the ramp rate of an output voltage for the charge pump during a recovery phase. The frequency of the clock is then adjusted so that the ramp rate of the output voltage for the charge pump during the recovery phase falls in a range not exceeding a predetermined maximum rate. A charge pump system is also described that includes a register having a settable value, where the charge pump clock frequency is responsive to the register value, and count and comparison circuitry is connectable to receive the pump's output voltage and the clock signal and determine from them the number of clock cycles the charge pump uses to recover from a reset value to a predetermined value.
摘要翻译：提出了一种设置包括时钟和电荷泵的电荷泵系统的时钟频率的方法。这包括设置时钟频率的初始值，并且在使用以初始频率值运行的时钟运行电荷泵系统的同时，在恢复阶段确定电荷泵的输出电压的斜坡率。然后调整时钟的频率，使得在恢复阶段期间电荷泵的输出电压的斜坡速率落在不超过预定最大速率的范围内。还描述了一种电荷泵系统，其包括具有可设置值的寄存器，其中电荷泵时钟频率响应于寄存器值，并且计数和比较电路可连接以接收泵的输出电压和时钟信号并从它们确定电荷泵用于从复位值恢复到预定值的时钟周期数。

7. 发明申请

WO2009085865A1 LOW NOISE SENSE AMPLIFIER ARRAY AND METHOD FOR NONVOLATILE MEMORY 审中-公开
标题翻译：低噪声感测放大器阵列和非易失性存储器的方法
公开(公告)号：WO2009085865A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/087262
申请日：2008-12-17
申请人： SANDISK CORPORATION , NGUYEN, Hao Thai , MUI, Man Lung , LEE, Seungpil
发明人： NGUYEN, Hao Thai , MUI, Man Lung , LEE, Seungpil
IPC分类号： G11C16/26 , G11C7/02 , G11C7/06
CPC分类号： G11C7/02 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/5642 , G11C16/26
摘要： In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.
摘要翻译：在感测具有对应的一组感测模块的非易失性存储器单元的页面中，当识别出每个高电流单元时，它被锁定以进一步检测，而页面中的其他单元继续被感测。被锁定的感测模块处于锁定模式并变为非活动状态。当处于锁定模式时，来自感测模块的噪声源变得显着。通过将其位线耦合到邻近单元，噪声容易干扰相邻单元的感测。噪声也可以通过页面的公共源行耦合，以影响页面中单元格的持续感测的准确性。改进的感测模块和方法将噪声与锁定感测模块隔离，以影响在页面中感测存储器单元中仍然有效的其他感测模块。

8. 发明申请

WO2008083132A3 COMPLETE WORD LINE LOOK AHEAD WITH EFFICIENT DATA LATCH ASSIGNMENT IN NON-VOLATILE MEMORY READ OPERATIONS 审中-公开
公开(公告)号：WO2008083132A3
公开(公告)日：2008-07-10
申请号：PCT/US2007/088779
申请日：2007-12-24
申请人： SANDISK CORPORATION , MUI, Man, Lung , LEE, Seungpil
发明人： MUI, Man, Lung , LEE, Seungpil
IPC分类号： G11C16/28
摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non- volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word line, the adjacent word line is read first and the data stored in a set of data latches for each bit line. One latch for each bit line stores an indication that the data is from the adjacent word line. The selected word line is then read with compensations based on the different states of the cells on the adjacent word line. Each sense module uses the data from the adjacent word line to select the results of sensing with the appropriate compensation for its bit line. The data from the adjacent word line is overwritten with data from the selected word line at the appropriate time and the indication updated to reflect that the latches store data from the selected word line. The efficient use of the data latches eliminates the need for separate latches to store data from the adjacent word line.

9. 发明申请

WO2008083132A2 COMPLETE WORD LINE LOOK AHEAD WITH EFFICIENT DATA LATCH ASSIGNMENT IN NON-VOLATILE MEMORY READ OPERATIONS 审中-公开
标题翻译：在非易失性存储器读取操作中使用有效的数据锁存指派完成字符行预测
公开(公告)号：WO2008083132A2
公开(公告)日：2008-07-10
申请号：PCT/US2007088779
申请日：2007-12-24
申请人： SANDISK CORP , MUI MAN LUNG , LEE SEUNGPIL
发明人： MUI MAN LUNG , LEE SEUNGPIL
IPC分类号： G11C16/28
CPC分类号： G11C11/5642 , G11C16/3418
摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non- volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word line, the adjacent word line is read first and the data stored in a set of data latches for each bit line. One latch for each bit line stores an indication that the data is from the adjacent word line. The selected word line is then read with compensations based on the different states of the cells on the adjacent word line. Each sense module uses the data from the adjacent word line to select the results of sensing with the appropriate compensation for its bit line. The data from the adjacent word line is overwritten with data from the selected word line at the appropriate time and the indication updated to reflect that the latches store data from the selected word line. The efficient use of the data latches eliminates the need for separate latches to store data from the adjacent word line.
摘要翻译：由于基于相邻单元存储的电荷的电场耦合，可能发生由非易失性存储器单元中的诸如浮置栅极的电荷存储区域存储的视在电荷的漂移。为了说明这种转变，阅读时应用补偿。当读取选定的字线时，首先读取相邻的字线，并且为每个位线读取存储在一组数据锁存器中的数据。每个位线的一个锁存器存储数据来自相邻字线的指示。然后根据相邻字线上单元的不同状态进行补偿读取所选字线。每个感测模块使用来自相邻字线的数据来选择对其位线进行适当补偿的感测结果。来自相邻字线的数据在适当的时间被来自所选字线的数据覆盖，并且更新指示以反映锁存器存储来自所选字线的数据。数据锁存器的有效使用消除了单独的锁存器来存储来自相邻字线的数据的需要。

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