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1. 发明申请

WO2011140057A1 MITIGATING CHANNEL COUPLING EFFECTS DURING SENSING OF NON-VOLATILE STORAGE ELEMENTS 审中-公开
标题翻译：在非易失存储元件感测期间减少通道耦合效应
公开(公告)号：WO2011140057A1
公开(公告)日：2011-11-10
申请号：PCT/US2011/034951
申请日：2011-05-03
申请人： SANDISK CORPORATION , DONG, Yingqa , LI, Yan , HSU, Cynthia
发明人： DONG, Yingqa , LI, Yan , HSU, Cynthia
IPC分类号： G11C11/56
CPC分类号： G11C11/5642 , G11C16/3418
摘要： Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established on bit lines when verifying each of a plurality of programmed states. A separate set of first bias conditions may be established when verifying each state. Biasing a bit line may be based on the state to which a non-volatile storage elements on the bit line is being programmed. A separate set of second bias conditions are established for each state being read. The second bias conditions for a given state substantially match the first bias conditions for the given state.
摘要翻译：通过匹配在读取期间发生的信道耦合量与验证期间发生的信道耦合，可以减轻非易失性存储的验证和读取期间的信道耦合效应。在验证和读取期间，所有位线都可以一起读取。在一个实施例中，当验证多个编程状态中的每一个时，在位线上建立第一偏置条件。当验证每个状态时，可以建立一组单独的第一偏置条件。偏置位线可以基于位线上的非易失性存储元件被编程的状态。为每个被读取的状态建立一组单独的第二偏置条件。给定状态的第二偏置条件基本上与给定状态的第一偏置条件相匹配。

2. 发明申请

WO2011005663A1 BAD COLUMN MANAGEMENT WITH BIT INFORMATION IN NON-VOLATILE MEMORY SYSTEMS 审中-公开
标题翻译：在非易失性存储系统中使用位信息的边栏管理
公开(公告)号：WO2011005663A1
公开(公告)日：2011-01-13
申请号：PCT/US2010/040828
申请日：2010-07-01
申请人： SANDISK CORPORATION , LI, Yan , KIM, Kwang-ho , TSAI, Frank W. , BOTTELLI, Aldo
发明人： LI, Yan , KIM, Kwang-ho , TSAI, Frank W. , BOTTELLI, Aldo
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G11C16/10 , G11C29/808
摘要： Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area.
摘要翻译：介绍了基于列的缺陷管理技术。存储器的每一列都有一个相关联的隔离锁存器或寄存器，其值表示列是否有缺陷，但是除了该信息之外，对于标记为有缺陷的列，使用附加信息来指示是否整个列被处理作为缺陷，或者列的单个位是否有缺陷。然后，可以基于该数据将有缺陷的元素重新映射到适当位或列级的冗余元件。当列是坏的但是仅在位电平时，好的位仍然可以用于数据，尽管这可以在对于某些位的编程的惩罚下完成，如下面进一步描述的。还描述了通过一组列测试来构建的用于收集位信息的自建内置自检（BIST）流程。基于该信息，可以通过控制器或存储器提取坏位并将其重新分组为字节，以更有效地使用列冗余区域。

3. 发明申请

WO2010042587A1 NONVOLATILE MEMORY AND METHOD WITH REDUCED PROGRAM VERIFY BY IGNORING FASTEST AND/OR SLOWEST PROGRAMMING BITS 审中-公开
标题翻译：非易失性存储器和方法通过点燃最慢和/或更慢的编程位置来减少程序验证
公开(公告)号：WO2010042587A1
公开(公告)日：2010-04-15
申请号：PCT/US2009/059799
申请日：2009-10-07
申请人： SANDISK CORPORATION , LI, Yan , FONG, Yupin, Kawing , CHAN, Siu Lung
发明人： LI, Yan , FONG, Yupin, Kawing , CHAN, Siu Lung
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

4. 发明申请

WO2009117204A1 ADAPTIVE ALGORITHM IN CACHE OPERATION WITH DYNAMIC DATA LATCH REQUIREMENTS 审中-公开
标题翻译：具有动态数据挂接要求的缓存操作中的自适应算法
公开(公告)号：WO2009117204A1
公开(公告)日：2009-09-24
申请号：PCT/US2009/034573
申请日：2009-02-19
申请人： SANDISK CORPORATION , LI, Yan , KOH, Anne Pao-Ling
发明人： LI, Yan , KOH, Anne Pao-Ling
IPC分类号： G11C16/10 , G11C7/10 , G11C11/56
CPC分类号： G11C16/10 , G06F12/0855 , G06F2212/2022 , G11C7/1039 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C11/5642 , G11C2207/2245 , G11C2211/5623 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed. The memory subsequently can perform the second operation during the first operation when a sufficient number of latches become available; and if, in response to determining whether there are a sufficient number of the corresponding set of data latches to perform the second operation it is determined that there are a sufficient number, performing the second operation during the first operation.
摘要翻译：非易失性存储器可以使用存储在相应的数据锁存器组中的第一组数据来执行一个或多个寻址页面的指定组上的第一操作（例如写入），并且还接收对还使用具有第二组数据的这些相应的数据锁存器中的一些的第二操作（例如读取）。在第一操作期间，当对应的每组的至少一个锁存器变得可用于第二操作时，存储器是否存在足够数量的对应的一组数据锁存器以在第一操作期间执行第二操作; 如果没有，则第二操作被延迟。当足够数量的锁存器变得可用时，存储器随后可以在第一操作期间执行第二操作; 并且如果响应于确定是否存在足够数量的对应的数据锁存器组来执行第二操作，则确定存在足够的数量，在第一操作期间执行第二操作。

5. 发明申请

WO2008033679A3 NON-VOLATILE MEMORY AND METHOD FOR REDUCED ERASE/WRITE CYCLING DURING TRIMMING OF INITIAL PROGRAMMING VOLTAGE 审中-公开
公开(公告)号：WO2008033679A3
公开(公告)日：2008-03-20
申请号：PCT/US2007/077295
申请日：2007-08-30
申请人： SANDISK CORPORATION , LI, Yan , TU, Loc , HOOK, Charles Moana
发明人： LI, Yan , TU, Loc , HOOK, Charles Moana
IPC分类号： G11C16/10 , G11C29/50
摘要： High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.

6. 发明申请

WO2008031074A1 PSEUDO RANDOM AND COMMAND DRIVEN BIT COMPENSATION FOR THE CYCLING EFFECTS IN FLASH MEMORY AND METHODS THEREFOR 审中-公开
标题翻译： FLASH存储器循环效应的PSEUDO随机和命令驱动位补偿及其方法
公开(公告)号：WO2008031074A1
公开(公告)日：2008-03-13
申请号：PCT/US2007/077940
申请日：2007-09-07
申请人： SANDISK CORPORATION , LI, Yan , FONG, Yupin Kawing
发明人： LI, Yan , FONG, Yupin Kawing
IPC分类号： G11C16/34 , G11C16/10 , G11C16/20 , G11C7/10 , G11C7/02 , G11C7/20
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/1039 , G11C7/1051 , G11C7/1063 , G11C7/20 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2207/2245
摘要： Easily implemented randomization within a flash memory EEPROM reduces the NAND string resistance effect, program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. The randomization may be code generated pseudo randomization or user driven randomization in different embodiments. User driven commands, the timing of which cannot be predicted may be used to trigger and achieve a high level of randomization. Randomly altering the encoding scheme of the data prevents repeated and long term storage of specific data patterns. Even if a user wishes to store the same information for long periods, or to repeatedly store it, it will be randomly encoded with different encoding schemes, and the data pattern will therefore be varied.
摘要翻译：易于实现的闪速存储器EEPROM内的随机化可以减少由于特定数据模式的重复和长期存储而导致的NAND串电阻效应，程序干扰，用户读取干扰以及浮动栅极到浮动栅极耦合。在不同的实施例中，随机化可以是代码生成的伪随机化或用户驱动的随机化。用户驱动的命令，其定时不能预测可用于触发并实现高水平的随机化。随机改变数据的编码方案可防止特定数据模式的重复和长期存储。即使用户希望长时间存储相同的信息，也可以重复存储，将以不同的编码方式进行随机编码，因此数据模式将会变化。

7. 发明申请

WO2007131127A3 MERGING QUEUED MEMORY OPERATION IN A NON-VOLATILE MEMORY 审中-公开
公开(公告)号：WO2007131127A3
公开(公告)日：2007-11-15
申请号：PCT/US2007/068172
申请日：2007-05-03
申请人： SANDISK CORPORATION , LI, Yan
发明人： LI, Yan
IPC分类号： G11C16/12 , G11C11/56
摘要： Methods and circuitry are present for executing current memory operation while other multiple pending memory operations are queued. Furthermore, when certain conditions are satisfied, some of these memory operations are combinable or mergeable for improved efficiency and other benefits. The management of the multiple memory operations is accomplished by the provision of a memory operation queue controlled by a memory operation queue manager. The memory operation queue manager is preferably implemented as a module in the state machine that controls the execution of a memory operation in the memory array.

8. 发明申请

WO2007076503A2 METHOD AND DEVICE FOR POWER-SAVING MULTI-PASS SENSING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中节省多通道感测的方法和装置
公开(公告)号：WO2007076503A2
公开(公告)日：2007-07-05
申请号：PCT/US2006/062605
申请日：2006-12-26
申请人： SANDISK CORPORATION , TSAO, Shou-Chang , LI, Yan
发明人： TSAO, Shou-Chang , LI, Yan
CPC分类号： G11C16/26
摘要： Power-saving techniques are employed in sensing a group of non-volatile memory cells in parallel. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will still be able to be detected in a subsequent pass.
摘要翻译：同时采用省电技术来感测一组非易失性存储单元。在一个方面，在预充电操作期间，存储器单元与它们的位线的耦合被延迟，以便减小单元电流抵抗预充电工作。在另一方面，通过在多遍感测操作中预先启动感测来使功耗预充电周期最小化。作为过早感测的结果，未检测到的高电流电流仍然能够在随后的通过中被检测。

9. 发明申请

WO2005029503A1 NON-VOLATILE MEMORY AND METHOD WITH BIT LINE COMPENSATION DEPENDENT ON NEIGHBORING OPERATING MODES 审中-公开
标题翻译：非挥发性记忆和方法与位线补偿依赖于邻近操作模式
公开(公告)号：WO2005029503A1
公开(公告)日：2005-03-31
申请号：PCT/US2004/030420
申请日：2004-09-16
申请人： SANDISK CORPORATION , KHALID, Shahzad , LI, Yan , CERNEA, Raul-Adrian , MOFIDI, Mehrdad
发明人： KHALID, Shahzad , LI, Yan , CERNEA, Raul-Adrian , MOFIDI, Mehrdad
IPC分类号： G11C16/34
CPC分类号： G11C16/3468 , G11C16/0483
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译：当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。偏移量作为电压偏移量加到编程中存储单元的位线。电压偏移是否是其邻居中的一个或两个或两个都处于产生扰动的模式中的预定函数，例如在程序禁止模式中。以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

10. 发明申请

WO2004029983A2 NON-VOLATILE MEMORY AND METHOD WITH REDUCED NEIGHBORING FIELD ERRORS 审中-公开
标题翻译：非易失性存储器和减少相邻现场错误的方法
公开(公告)号：WO2004029983A2
公开(公告)日：2004-04-08
申请号：PCT/US2003/029045
申请日：2003-09-18
申请人： SANDISK CORPORATION
发明人： CERNEA, Raul-Adrian , LI, Yan
IPC分类号： G11C16/10
CPC分类号： G11C16/3459 , G11C8/08 , G11C8/10 , G11C11/5628 , G11C16/26 , G11C16/3418 , G11C16/3454
摘要： A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same word line and a read/write circuit is coupled to each memory cells in a contiguous manner. Thus, a memory cell and its neighbors are programmed together and the field environment for each memory cell relative to its neighbors during programming and subsequent reading is less varying. This improves performance and reduces errors caused by coupling from fields of neighboring cells, as compared to conventional architectures and methods in which cells on even columns are programmed independently of cells in odd columns.
摘要翻译：存储器件及其方法允许并行地编程和感测多个存储器单元，以便最小化由相邻单元的场的耦合引起的误差并提高性能。存储器件和方法具有通过相同字线链接的多个存储器单元，并且读/写电路以连续的方式耦合到每个存储器单元。因此，存储器单元及其邻居被编程在一起，并且在编程和随后读取期间，每个存储器单元相对于其邻居的现场环境变化较小。与传统架构和偶数列上的单元格独立于奇数列中的单元进行编程的方法相比，这提高了性能并减少了从相邻单元的字段耦合引起的错误。

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