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1. 发明申请

WO2005031753A1 ERASE INHIBIT IN NON-VOLATILE MEMORIES 审中-公开
标题翻译：消除非易失性存储器中的消除
公开(公告)号：WO2005031753A1
公开(公告)日：2005-04-07
申请号：PCT/US2004/031082
申请日：2004-09-21
申请人： SANDISK CORPORATION , QUADER, Khandker, N. , CERNEA, Raul-Adrian
发明人： QUADER, Khandker, N. , CERNEA, Raul-Adrian
IPC分类号： G11C16/14
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/3418
摘要： The present invention presents a non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process. For a set of storage elements formed over a common well structure, all word-lines are initially charged with the same high voltage erase signal that charges the well to insure there is no net voltage difference between the well and word-lines. The selected word-lines are then discharged to ground while the non-selected word-lines and the well are maintained at the high voltage. According to another aspect of the present invention, this can be accomplished without increasing any pitch area circuit or adding new wires in the memory array, and at minimal additional peripheral area. Advantages include less potential erase disturb in the non-selected storage elements and a tighter erase distribution for the selected elements.
摘要翻译：本发明提供一种用于其操作的非易失性存储器和方法，其可以在擦除处理期间减少未选择的单元的干扰量。对于在公共阱结构上形成的一组存储元件，所有字线最初都以相同的高电压擦除信号充电，以确保阱和字线之间没有净电压差。所选择的字线然后放电到地，而未选择的字线和阱保持在高电压。根据本发明的另一方面，这可以在不增加任何音调区域电路或在存储器阵列中添加新的线以及在最小额外周边区域的情况下实现。优点包括在未选择的存储元件中较少的电位擦除干扰以及所选元件的更严格的擦除分布。

2. 发明申请

WO2005029503A1 NON-VOLATILE MEMORY AND METHOD WITH BIT LINE COMPENSATION DEPENDENT ON NEIGHBORING OPERATING MODES 审中-公开
标题翻译：非挥发性记忆和方法与位线补偿依赖于邻近操作模式
公开(公告)号：WO2005029503A1
公开(公告)日：2005-03-31
申请号：PCT/US2004/030420
申请日：2004-09-16
申请人： SANDISK CORPORATION , KHALID, Shahzad , LI, Yan , CERNEA, Raul-Adrian , MOFIDI, Mehrdad
发明人： KHALID, Shahzad , LI, Yan , CERNEA, Raul-Adrian , MOFIDI, Mehrdad
IPC分类号： G11C16/34
CPC分类号： G11C16/3468 , G11C16/0483
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译：当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。偏移量作为电压偏移量加到编程中存储单元的位线。电压偏移是否是其邻居中的一个或两个或两个都处于产生扰动的模式中的预定函数，例如在程序禁止模式中。以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

3. 发明申请

WO2005017902A1 AREA EFFICIENT CHARGE PUMP 审中-公开
标题翻译：区域有效充电泵
公开(公告)号：WO2005017902A1
公开(公告)日：2005-02-24
申请号：PCT/US2004/024064
申请日：2004-07-27
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian
发明人： CERNEA, Raul-Adrian
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , H02M3/073
摘要： A first charge pump includes a collection of voltage adder stages. The first voltage adder stage receives an input voltage VCC and in response to a clock signal provides a first voltage signal alternating between 2*VCC and VCC. The Nth voltage adder stage receives an input voltage VCC and a first voltage signal from the preceding stage, and provides a second voltage signal alternating between N*VCC and VCC. The capacitors included within each adder stage are required to sustain a maximum voltage of VCC. In an alternate embodiment the first charge pump may be combined with one or more voltage doubler stages to produce even higher output voltages.
摘要翻译：第一电荷泵包括电压加法器级的集合。第一电压加法级接收输入电压VCC，响应于时钟信号，提供在2 * VCC和VCC之间交替的第一电压信号。第N电压加法级接收来自前级的输入电压VCC和第一电压信号，并提供在N * VCC和VCC之间交替的第二电压信号。包括在每个加法器级内的电容器需要维持VCC的最大电压。在替代实施例中，第一电荷泵可以与一个或多个倍压器级组合以产生更高的输出电压。

4. 发明申请

WO2004029983A2 NON-VOLATILE MEMORY AND METHOD WITH REDUCED NEIGHBORING FIELD ERRORS 审中-公开
标题翻译：非易失性存储器和减少相邻现场错误的方法
公开(公告)号：WO2004029983A2
公开(公告)日：2004-04-08
申请号：PCT/US2003/029045
申请日：2003-09-18
申请人： SANDISK CORPORATION
发明人： CERNEA, Raul-Adrian , LI, Yan
IPC分类号： G11C16/10
CPC分类号： G11C16/3459 , G11C8/08 , G11C8/10 , G11C11/5628 , G11C16/26 , G11C16/3418 , G11C16/3454
摘要： A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same word line and a read/write circuit is coupled to each memory cells in a contiguous manner. Thus, a memory cell and its neighbors are programmed together and the field environment for each memory cell relative to its neighbors during programming and subsequent reading is less varying. This improves performance and reduces errors caused by coupling from fields of neighboring cells, as compared to conventional architectures and methods in which cells on even columns are programmed independently of cells in odd columns.
摘要翻译：存储器件及其方法允许并行地编程和感测多个存储器单元，以便最小化由相邻单元的场的耦合引起的误差并提高性能。存储器件和方法具有通过相同字线链接的多个存储器单元，并且读/写电路以连续的方式耦合到每个存储器单元。因此，存储器单元及其邻居被编程在一起，并且在编程和随后读取期间，每个存储器单元相对于其邻居的现场环境变化较小。与传统架构和偶数列上的单元格独立于奇数列中的单元进行编程的方法相比，这提高了性能并减少了从相邻单元的字段耦合引起的错误。

5. 发明申请

WO2003067437A1 MEMORY MAPPING DEVICE UTILIZING SECTOR POINTERS 审中-公开
标题翻译：存储器映射设备利用部门指针
公开(公告)号：WO2003067437A1
公开(公告)日：2003-08-14
申请号：PCT/US2003/003418
申请日：2003-02-04
申请人： SANDISK CORPORATION
发明人： CERNEA, Raul-Adrian
IPC分类号： G06F12/02
CPC分类号： G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7201 , G11C15/00
摘要： A pointer structure on the storage unit of a non-volatile memory maintains a correspondence between the physical and logical address. The controller (101) and storage unit transfer data on the basis of logical sector addresses with the conversion between the physical and logical addresses being performed on the storage unit. The pointer structure (110) contains a correspondence between a logical sector address and the physical address of current data as well as maintaining one or more previous correspondences between the logical address and the physical addresses at which old data is stored. In an exemplary embodiment, the pointer structure (110) is one or more independent non-volatile sub-arrays, each with its own row decoder (303a, 303b). Each pointer has a flag to indicate if it is active in addition to storing the current correspondence between a logical address and a physical address and one or more previous correspondences.
摘要翻译：非易失性存储器的存储单元上的指针结构维持物理和逻辑地址之间的对应关系。控制器（101）和存储单元基于在存储单元上执行的物理和逻辑地址之间的转换的逻辑扇区地址来传送数据。指针结构（110）包含逻辑扇区地址和当前数据的物理地址之间的对应关系，以及保持逻辑地址与存储旧数据的物理地址之间的一个或多个先前的对应关系。在示例性实施例中，指针结构（110）是一个或多个独立的非易失性子阵列，每个具有其自己的行解码器（303a，303b）。除了存储逻辑地址和物理地址之间的当前对应以及一个或多个先前的通信之外，每个指针都有一个标志来指示它是否处于活动状态。

6. 发明申请

WO2003041082A1 NON-VOLATILE MEMORY WITH TEMPERATURE-COMPENSATED DATA READ 审中-公开
标题翻译：具有温度补偿数据读数的非易失性存储器
公开(公告)号：WO2003041082A1
公开(公告)日：2003-05-15
申请号：PCT/US2002/034236
申请日：2002-10-24
申请人： SANDISK CORPORATION
发明人： CERNEA, Raul-Adrian
IPC分类号： G11C
CPC分类号： G11C7/04 , G11C7/12 , G11C16/26 , G11C16/28
摘要： A novel non-volatile memory is disclosed. The non-volatile memory including an array of data storage cells that individually include a storage element (43) such as a floating gate, a control gate and first and second source/drain terminals. A current source (61) provides a current to the first source/drain terminal of the data storage element. A node (75) is electrically connected to the second source/drain terminal of the data storage element. A bias circuit (73, 69) provides a bias voltage to the node. The bias voltage varies with temperature in a manner approximately inverse to the thermal variation of the threshold voltage of the data storage element. A control gate voltage circuit provides a voltage level to the control gate of the data storage cell.
摘要翻译：公开了一种新颖的非易失性存储器。该非易失性存储器包括单独地包括诸如浮动栅极，控制栅极和第一和第二源极/漏极端子的存储元件（43）的数据存储单元阵列。电流源（61）向数据存储元件的第一源极/漏极端子提供电流。节点（75）电连接到数据存储元件的第二源极/漏极端子。偏置电路（73,69）向节点提供偏置电压。偏置电压以与数据存储元件的阈值电压的热变化大致相反的方式随温度变化。控制栅极电压电路向数据存储单元的控制栅极提供电压电平。

7. 发明申请

WO2006107706A1 NON-VOLATILE MEMORY AND METHOD WITH COMPENSATION FOR SOURCE LINE BIAS ERRORS 审中-公开
标题翻译：非易失性存储器和补偿源线偏差的方法
公开(公告)号：WO2006107706A1
公开(公告)日：2006-10-12
申请号：PCT/US2006/011675
申请日：2006-03-29
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian , CHAN, Siu Lung
发明人： CERNEA, Raul-Adrian , CHAN, Siu Lung
IPC分类号： G11C16/30 , G11C5/14
CPC分类号： G11C16/30 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1078 , G11C7/12
摘要： Source line bias (virtual ground) is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
摘要翻译：源极偏置（虚地）是由读/写电路的接地回路中的非零电阻引入的误差。在感测期间，存储器单元的源极被电阻两端的电压降错误地偏置，并导致施加的控制栅极和漏极电压的误差。当施加的控制栅极和漏极电压的参考点尽可能靠近存储器单元的源极时，该误差被最小化。在一个优选实施例中，参考点位于施加源极控制信号的节点处。当存储器阵列被组织在并行感测的存储器单元的页面中时，每个页面中的源耦合到页面源行，参考点被选择为经由复用器处于所选页面的页面源行。

8. 发明申请

WO2006107633A1 USE OF DATA LATCHES IN MULTI-PHASE PROGRAMMING OF NON-VOLATILE MEMORIES 审中-公开
标题翻译：数据锁存器在非易失性存储器的多阶段编程中的应用
公开(公告)号：WO2006107633A1
公开(公告)日：2006-10-12
申请号：PCT/US2006/011032
申请日：2006-03-27
申请人： SANDISK CORPORATION , LI, Yan , CERNEA, Raul-Adrian
发明人： LI, Yan , CERNEA, Raul-Adrian
IPC分类号： G11C16/34
CPC分类号： G11C16/3468
摘要： A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.
摘要翻译：非易失性存储器件包括用于在非易失性存储器中控制多相编程过程的电路。示例性实施例使用快速通过写入技术，其中使用单个编程遍，但是当存储器单元通过提高所选存储器的通道的电压电平接近其目标值时，选择的存储器单元的偏置被改变为慢编程细胞。本发明的一个主要方面引入一个与可读取/写入电路相关联的锁存器，该读取/写入电路可以沿着相应的位线连接到每个选定的存储器单元，以便在该较低级别存储验证结果。

9. 发明申请

WO2004029984A2 NON-VOLATILE MEMORY AND METHOD WITH IMPROVED SENSING 审中-公开
标题翻译：非易失性存储器和具有改进感测的方法
公开(公告)号：WO2004029984A2
公开(公告)日：2004-04-08
申请号：PCT/US2003/029603
申请日：2003-09-23
申请人： SANDISK CORPORATION
发明人： CERNEA, Raul-Adrian , LI, Yan
IPC分类号： G11C16/26
CPC分类号： G11C7/062 , G11C7/067 , G11C11/5642 , G11C16/26
摘要： Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.
摘要翻译：源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。在感测期间，存储器单元的控制栅极电压被跨过电阻的电压降错误地偏置。当通过接地回路的电流减小时，该误差被最小化。用于减少源极偏置的方法是通过具有用于多通感测的特征和技术的读/写电路实现的。当并行地检测到一页存储单元时，每次通过有助于识别和关闭具有高于给定分界电流值的传导电流的存储单元。特别地，在当前通路中的所有感测完成之后，所识别的存储器单元关闭。以这种方式，关闭操作不会影响感测操作。在后续通过中的感测将受到源极偏置的影响较小，因为通过消除较高电流单元的贡献，电流流动的总量显着减少。在感测改进的另一方面，采用参考读出放大器来控制多个读出放大器以减少它们对电源和环境变化的依赖。

10. 发明申请

WO2002097820A2 DUAL CELL READING AND WRITING TECHNIQUE 审中-公开
标题翻译：双电池读写技术
公开(公告)号：WO2002097820A2
公开(公告)日：2002-12-05
申请号：PCT/US2002/016835
申请日：2002-05-29
申请人： SANDISK CORPORATION
发明人： CERNEA, Raul-Adrian
IPC分类号： G11C
CPC分类号： G11C16/10 , G11C16/0491 , G11C16/26
摘要： The cells of a memory cell array are programmed in a pair wise manner. The pairs are separated by at least one memory cell, reducing the possibility of interference between the pairs during programming. The memory cells are programmed individually by applying a relatively high voltage to one of the bit lines of each cell regardless whether the cells are to be programmed or not, while applying a lower voltage to the second bit lines, depending on whether the cells are to be programmed or not. This programming voltage assignment enhances the speed of programming. Furthermore, the pair wise programming scheme applies the necessary high voltages only half as often as in previous schemes to program all the cells of the array, increasing the lifetime of the memory system.
摘要翻译：存储单元阵列的单元以成对的方式编程。这些对由至少一个存储器单元隔开，从而减少编程期间对之间干扰的可能性。通过对每个单元的位线之一施加相对较高的电压，而不管单元是否被编程，同时对第二位线施加较低的电压，取决于单元是否要是否被编程。该编程电压分配提高了编程速度。此外，成对的编程方案将必要的高电压仅与先前的方案一样频繁地编程阵列的所有单元，增加了存储器系统的使用寿命。

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