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1. 发明申请

WO2005029503A1 NON-VOLATILE MEMORY AND METHOD WITH BIT LINE COMPENSATION DEPENDENT ON NEIGHBORING OPERATING MODES 审中-公开
标题翻译：非挥发性记忆和方法与位线补偿依赖于邻近操作模式
公开(公告)号：WO2005029503A1
公开(公告)日：2005-03-31
申请号：PCT/US2004/030420
申请日：2004-09-16
申请人： SANDISK CORPORATION , KHALID, Shahzad , LI, Yan , CERNEA, Raul-Adrian , MOFIDI, Mehrdad
发明人： KHALID, Shahzad , LI, Yan , CERNEA, Raul-Adrian , MOFIDI, Mehrdad
IPC分类号： G11C16/34
CPC分类号： G11C16/3468 , G11C16/0483
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译：当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。偏移量作为电压偏移量加到编程中存储单元的位线。电压偏移是否是其邻居中的一个或两个或两个都处于产生扰动的模式中的预定函数，例如在程序禁止模式中。以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

2. 发明申请

WO2005029502A1 NON-VOLATILE MEMORY AND METHOD WITH BIT LINE TO BIT LINE COUPLED COMPENSATION 审中-公开
标题翻译：非线性记忆和方法与位线对位线联合补偿
公开(公告)号：WO2005029502A1
公开(公告)日：2005-03-31
申请号：PCT/US2004/029426
申请日：2004-09-08
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian , LI, Yan , MOFIDI, Mehrdad , KHALID, Shahzad
发明人： CERNEA, Raul-Adrian , LI, Yan , MOFIDI, Mehrdad , KHALID, Shahzad
IPC分类号： G11C16/34
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C16/3468
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译：当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

3. 发明申请

WO2006107633A1 USE OF DATA LATCHES IN MULTI-PHASE PROGRAMMING OF NON-VOLATILE MEMORIES 审中-公开
标题翻译：数据锁存器在非易失性存储器的多阶段编程中的应用
公开(公告)号：WO2006107633A1
公开(公告)日：2006-10-12
申请号：PCT/US2006/011032
申请日：2006-03-27
申请人： SANDISK CORPORATION , LI, Yan , CERNEA, Raul-Adrian
发明人： LI, Yan , CERNEA, Raul-Adrian
IPC分类号： G11C16/34
CPC分类号： G11C16/3468
摘要： A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.
摘要翻译：非易失性存储器件包括用于在非易失性存储器中控制多相编程过程的电路。示例性实施例使用快速通过写入技术，其中使用单个编程遍，但是当存储器单元通过提高所选存储器的通道的电压电平接近其目标值时，选择的存储器单元的偏置被改变为慢编程细胞。本发明的一个主要方面引入一个与可读取/写入电路相关联的锁存器，该读取/写入电路可以沿着相应的位线连接到每个选定的存储器单元，以便在该较低级别存储验证结果。

4. 发明申请

WO2005066975A1 FLEXIBLE AND AREA EFFICIENT COLUMN REDUNDANCY FOR NON-VOLATILE MEMORIES 审中-公开
标题翻译：灵活和有效的色谱柱冗余非挥发性记忆
公开(公告)号：WO2005066975A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/042990
申请日：2004-12-20
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian , LI, Yan
发明人： CERNEA, Raul-Adrian , LI, Yan
IPC分类号： G11C29/00
CPC分类号： G11C7/1036 , G11C29/848
摘要： The present invention presents a non-volatile memory wherein bad columns in the array of memory cells can be removed. According to another aspect of the present invention, substitute redundant columns can replace the removed columns. Both of these processes are performed on the memory in a manner that is externally transparent and, consequently, need not be managed externally by the host or controller to which the memory is attached. An inventory of the bad columns can be maintained on the memory. At power up, the list of bad columns is used to fuse out the bad columns. The memory may also contain a number of redundant columns that can be used to replace the bad columns.
摘要翻译：本发明提供了一种非易失性存储器，其中可以去除存储器单元阵列中的不良列。根据本发明的另一方面，替代冗余列可以替代所移除的列。这些处理都以外部透明的方式在存储器上执行，因此不需要由附加存储器的主机或控制器在外部进行管理。可以在内存上维护坏列的清单。上电时，不良列的列表用于对不良列进行融合。内存还可能包含一些可用于替换不良列的冗余列。

5. 发明申请

WO2005031753A1 ERASE INHIBIT IN NON-VOLATILE MEMORIES 审中-公开
标题翻译：消除非易失性存储器中的消除
公开(公告)号：WO2005031753A1
公开(公告)日：2005-04-07
申请号：PCT/US2004/031082
申请日：2004-09-21
申请人： SANDISK CORPORATION , QUADER, Khandker, N. , CERNEA, Raul-Adrian
发明人： QUADER, Khandker, N. , CERNEA, Raul-Adrian
IPC分类号： G11C16/14
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/3418
摘要： The present invention presents a non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process. For a set of storage elements formed over a common well structure, all word-lines are initially charged with the same high voltage erase signal that charges the well to insure there is no net voltage difference between the well and word-lines. The selected word-lines are then discharged to ground while the non-selected word-lines and the well are maintained at the high voltage. According to another aspect of the present invention, this can be accomplished without increasing any pitch area circuit or adding new wires in the memory array, and at minimal additional peripheral area. Advantages include less potential erase disturb in the non-selected storage elements and a tighter erase distribution for the selected elements.
摘要翻译：本发明提供一种用于其操作的非易失性存储器和方法，其可以在擦除处理期间减少未选择的单元的干扰量。对于在公共阱结构上形成的一组存储元件，所有字线最初都以相同的高电压擦除信号充电，以确保阱和字线之间没有净电压差。所选择的字线然后放电到地，而未选择的字线和阱保持在高电压。根据本发明的另一方面，这可以在不增加任何音调区域电路或在存储器阵列中添加新的线以及在最小额外周边区域的情况下实现。优点包括在未选择的存储元件中较少的电位擦除干扰以及所选元件的更严格的擦除分布。

6. 发明申请

WO2005017902A1 AREA EFFICIENT CHARGE PUMP 审中-公开
标题翻译：区域有效充电泵
公开(公告)号：WO2005017902A1
公开(公告)日：2005-02-24
申请号：PCT/US2004/024064
申请日：2004-07-27
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian
发明人： CERNEA, Raul-Adrian
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , H02M3/073
摘要： A first charge pump includes a collection of voltage adder stages. The first voltage adder stage receives an input voltage VCC and in response to a clock signal provides a first voltage signal alternating between 2*VCC and VCC. The Nth voltage adder stage receives an input voltage VCC and a first voltage signal from the preceding stage, and provides a second voltage signal alternating between N*VCC and VCC. The capacitors included within each adder stage are required to sustain a maximum voltage of VCC. In an alternate embodiment the first charge pump may be combined with one or more voltage doubler stages to produce even higher output voltages.
摘要翻译：第一电荷泵包括电压加法器级的集合。第一电压加法级接收输入电压VCC，响应于时钟信号，提供在2 * VCC和VCC之间交替的第一电压信号。第N电压加法级接收来自前级的输入电压VCC和第一电压信号，并提供在N * VCC和VCC之间交替的第二电压信号。包括在每个加法器级内的电容器需要维持VCC的最大电压。在替代实施例中，第一电荷泵可以与一个或多个倍压器级组合以产生更高的输出电压。

7. 发明申请

WO2006107706A1 NON-VOLATILE MEMORY AND METHOD WITH COMPENSATION FOR SOURCE LINE BIAS ERRORS 审中-公开
标题翻译：非易失性存储器和补偿源线偏差的方法
公开(公告)号：WO2006107706A1
公开(公告)日：2006-10-12
申请号：PCT/US2006/011675
申请日：2006-03-29
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian , CHAN, Siu Lung
发明人： CERNEA, Raul-Adrian , CHAN, Siu Lung
IPC分类号： G11C16/30 , G11C5/14
CPC分类号： G11C16/30 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1078 , G11C7/12
摘要： Source line bias (virtual ground) is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
摘要翻译：源极偏置（虚地）是由读/写电路的接地回路中的非零电阻引入的误差。在感测期间，存储器单元的源极被电阻两端的电压降错误地偏置，并导致施加的控制栅极和漏极电压的误差。当施加的控制栅极和漏极电压的参考点尽可能靠近存储器单元的源极时，该误差被最小化。在一个优选实施例中，参考点位于施加源极控制信号的节点处。当存储器阵列被组织在并行感测的存储器单元的页面中时，每个页面中的源耦合到页面源行，参考点被选择为经由复用器处于所选页面的页面源行。

8. 发明申请

WO2009151894A1 NONVOLATILE MEMORY AND METHOD WITH INDEX PROGRAMMING AND REDUCED VERIFY 审中-公开
标题翻译：非易失性存储器和方法与索引编程和减少的验证
公开(公告)号：WO2009151894A1
公开(公告)日：2009-12-17
申请号：PCT/US2009/044554
申请日：2009-05-19
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian
发明人： CERNEA, Raul-Adrian
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.
摘要翻译：在非易失性存储器中，使用多通道索引编程方法将一组存储器单元分别编程到其目标状态，这减少了验证步骤的数量。对于每个单元，程序索引保持存储施加到单元的最后编程电压。在第一次编程过程中，每个单元都应用一系列增量编程脉冲进行索引。第一个编程通过之后是验证和一个或多个后续编程传递，以修剪对各个目标状态的任何短暂的下降。如果单元无法验证到其目标状态，则其程序索引增加，并允许通过来自最后接收的脉冲的下一个脉冲对单元进行编程。重复验证和编程遍历，直到组中的所有单元格被验证到其各自的目标状态。不需要脉冲之间的验证操作。

9. 发明申请

WO2007112202A2 NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN REMOTE BUFFER CIRCUITS 审中-公开
标题翻译：非易失性存储器和冗余数据在远程缓冲器电路中缓冲的方法
公开(公告)号：WO2007112202A2
公开(公告)日：2007-10-04
申请号：PCT/US2007/063912
申请日：2007-03-13
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian
发明人： CERNEA, Raul-Adrian
IPC分类号： G11C29/00 , G11C16/26
CPC分类号： G11C7/106 , G11C7/1039 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C16/04 , G11C29/846
摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has the redundant data available from a central buffer accessible by any number of column circuits. Redundant data buffer circuits enable bus exchange with data from the user data latches except for defective locations when data are taken from the central buffer. In this way only addressing for the user portion is used for bus exchange. Also, accessibility to the redundant data will not be restricted by the locations of the column circuits relative to the redundant data latches and the buffered redundant data can be accessed at a finer granularity than that imposed by the column circuits.
摘要翻译：存储器在其用户部分具有可由冗余部分中的冗余位置替换的缺陷位置。用户和冗余部分的列电路中的数据锁存器允许从存储器读出或写入存储器的数据与数据总线交换。远程冗余方案具有从任何数量的列电路可访问的中央缓冲器提供的冗余数据。冗余数据缓冲电路使用来自用户数据锁存器的数据进行总线交换，除了从中央缓冲器获取数据时的缺陷位置。以这种方式，仅对用户部分进行寻址用于总线交换。此外，冗余数据的可访问性不会受到列电路相对于冗余数据锁存器的位置的限制，并且可以以比列电路施加的更精细的粒度访问缓冲的冗余数据。

10. 发明申请

WO2007112201A3 NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN DATA LATCHES FOR DEFECTIVE LOCATIONS 审中-公开
公开(公告)号：WO2007112201A3
公开(公告)日：2007-10-04
申请号：PCT/US2007/063863
申请日：2007-03-13
申请人： SANDISK CORPORATION , MOOGAT, Farookh , CERNEA, Raul-Adrian , TSAO, Shou-Chang , TSENG, Tai-Yuan
发明人： MOOGAT, Farookh , CERNEA, Raul-Adrian , TSAO, Shou-Chang , TSENG, Tai-Yuan
IPC分类号： G11C29/00 , G11C16/26
摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

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