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1. 发明申请

WO2006107409A3 DECODING CIRCUIT FOR NON-BINARY GROUPS OF MEMORY LINE DRIVERS 审中-公开
标题翻译：解码存储线驱动器非二进制组的电路
公开(公告)号：WO2006107409A3
公开(公告)日：2007-04-19
申请号：PCT/US2006005067
申请日：2006-02-14
申请人： SANDISK , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , FASOLI LUCA G
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C5/063 , G11C8/08 , G11C8/14
摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.
摘要翻译：公开了一种用于非二进制组的存储器线驱动器的解码电路。在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一。控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。本文所述的概念可以单独使用或组合使用。

2. 发明申请

WO2008016950A3 METHOD AND APPARATUS FOR MEMORY ARRAY INCORPORATING TWO DATA BUSSES FOR MEMORY ARRAY BLOCK SELECTION 审中-公开
标题翻译：用于存储阵列选择的两个数据总线的存储器阵列的方法和装置
公开(公告)号：WO2008016950A3
公开(公告)日：2008-05-02
申请号：PCT/US2007074903
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , FASOLI LUCA G , PETTI CHRISTOPHER J
发明人： SCHEUERLEIN ROY E , FASOLI LUCA G , PETTI CHRISTOPHER J
IPC分类号： G11C7/10 , G11C8/10 , G11C8/12
CPC分类号： G11C17/18 , G11C5/063 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14
摘要： Circuits and methods (370) are described for decoding exemplary memory arrays (374, 375) of programmable, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods (370) are described for selecting one or more array blocks (374, 375) of such a memory array, for selecting one or more word lines (377) and bit lines within selected array blocks (374, 375), for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselecte array blocks.
摘要翻译：描述了用于解码可编程可重写无源元件存储单元的示例性存储器阵列（374,375）的电路和方法（370），其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。另外，描述了用于选择这种存储器阵列的一个或多个阵列块（374,375）的电路和方法（370），用于选择一个或多个字线（377）和选定阵列块（374,375）内的位线），用于将数据信息传送到所选择的阵列块内的所选择的存储器单元，以及用于传送未选择的偏置条件以取消选择阵列块。

3. 发明申请

WO2008016932A2 METHOD AND APPARATUS FOR PASSIVE ELEMENT MEMORY ARRAY INCORPORATING REVERSIBLE POLARITY WORD LINE AND BIT LINE DECODERS 审中-公开
标题翻译：包含可逆极性字线和位线解码器的被动元件存储器阵列的方法和设备
公开(公告)号：WO2008016932A2
公开(公告)日：2008-02-07
申请号：PCT/US2007074883
申请日：2007-07-31
申请人： SANDISK 3D LLC , FASOLI LUCA G , PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
发明人： FASOLI LUCA G , PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C8/08 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程和在一些实施例中的可重写无源元件存储器单元的示例性存储器阵列的电路和方法，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。另外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择选定阵列块内的一个或多个字线和位线，用于向选定阵列块内的选定存储器单元传送数据信息并且用于将未选择的偏置条件传送给未选择的阵列块。

4. 发明申请

WO2008016946A3 METHOD AND APPARATUS FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY 审中-公开
标题翻译：用于读取多级被动元件存储单元阵列的方法和装置
公开(公告)号：WO2008016946A3
公开(公告)日：2009-01-08
申请号：PCT/US2007074899
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , THORP TYLER J , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , THORP TYLER J , FASOLI LUCA G
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C11/5642 , G11C13/004 , G11C13/0069 , G11C16/24 , G11C16/26 , G11C2013/0054 , G11C2013/009 , G11C2211/5634 , G11C2213/77
摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
摘要翻译：四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选地分别映射到数据状态11,01,00和10. LSB和MSB优选地被映射为不同页面的一部分。为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。中间级参考用于读取LSB。当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

5. 发明申请

WO2008016948A3 DUAL DATA-DEPENDENT BUSSES FOR COUPLING READ/WRITE CIRCUITS TO A MEMORY ARRAY 审中-公开
标题翻译：用于将读/写电路耦合到存储阵列的双数据相关总线
公开(公告)号：WO2008016948A3
公开(公告)日：2009-01-08
申请号：PCT/US2007074901
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , FASOLI LUCA G
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1048 , G11C7/18 , G11C8/08
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

6. 发明申请

WO2006105453A2 INTEGRATED CIRCUIT MEMORY ARRAY CONFIGURATION INCLUDING DECODING COMPATIBILITY WITH PARTIAL IMPLEMENTATION OF MULTIPLE MEMORY LAYERS 审中-公开
标题翻译：集成电路存储器阵列配置，包括解码兼容性，实现多个存储层的部分实现
公开(公告)号：WO2006105453A2
公开(公告)日：2006-10-05
申请号：PCT/US2006012106
申请日：2006-03-31
申请人： SANDISK 3D LLC , FASOLI LUCA G , SCHEUERLEIN ROY E
发明人： FASOLI LUCA G , SCHEUERLEIN ROY E
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C7/18 , G11C29/808 , H01L27/101 , H01L27/105 , Y10T29/49002
摘要： An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.
摘要翻译：具有三维存储器阵列的集成电路提供给定数量的存储器平面，但是可以通过省略与省略的存储器平面相关联的掩模和处理步骤来代替地包括较少数量的存储器层，而不改变任何用于其他存储器平面或其余设备的其他制造掩模，并且不需要对阵列的读取或读取/写入路径进行路由或其他配置更改。用于选择性地启用某些层选择器电路的控制电路是可配置的，并且层选择器电路被适当地布置，以将实现的存储器层上的相应阵列线耦合到每个相应的I / O总线，而与所实现的存储器平面的数量无关。

7. 发明申请

WO2006121529A3 METHOD AND APPARATUS FOR INCORPORATING BLOCK REDUNDANCY IN A MEMORY ARRAY 审中-公开
标题翻译：在存储阵列中加入块冗余的方法和装置
公开(公告)号：WO2006121529A3
公开(公告)日：2007-08-02
申请号：PCT/US2006012107
申请日：2006-03-31
申请人： SANDISK 3D LLC , FASOLI LUCA G , SCHEUERLEIN ROY E
发明人： FASOLI LUCA G , SCHEUERLEIN ROY E
IPC分类号： G11C16/04
CPC分类号： G11C29/808 , G11C29/76 , G11C29/804 , G11C29/816
摘要： An integrated circuit memory array includes alternating first and second types of memory blocks, each memory block including respective array lines shared with a respective array line in an adjacent memory block. The array lines of a defective block of one type are mapped into a spare block of the same type. The array lines of a first adjacent block which are shared with array lines of the defective block, and the array lines of a second adjacent block which are shared with array lines of the defective block, are mapped into a second spare block of the other type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.
摘要翻译：集成电路存储器阵列包括交替的第一和第二类型的存储块，每个存储块包括与相邻存储器块中的相应阵列线共享的相应阵列线。一种类型的缺陷块的阵列线被映射到相同类型的备用块。与缺陷块的阵列线共享的第一相邻块的阵列线和与缺陷块的阵列线共享的第二相邻块的阵列线被映射到另一种类型的第二备用块从而将缺陷块和两个相邻块的部分映射到仅两个备用块中。

8. 发明申请

WO2008016951A3 METHOD AND APPARATUS FOR HIERARCHICAL BIT LINE BIAS BUS FOR BLOCK SELECTABLE MEMORY ARRAY 审中-公开
标题翻译：用于块选择存储器阵列的分层位线偏置总线的方法和装置
公开(公告)号：WO2008016951A3
公开(公告)日：2008-05-15
申请号：PCT/US2007074904
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , FASOLI LUCA G
IPC分类号： G11C8/00 , G11C11/34
CPC分类号： G11C17/16 , G11C7/1048 , G11C7/12 , G11C7/18 , G11C8/12 , G11C13/0026 , G11C13/02 , G11C17/18 , G11C2207/002 , G11C2213/71
摘要： Circuits [154 of figure 3] and methods are described for decoding exemplary memory arrays of programmable [100 of figure 1] and, in some embodiments, re-writable passive element memory cells [101 of figure 1], which are particularly useful for extremely dense three dimensional memory arrays having more than one memory plane [figure 12] In addition, circuits and methods are descpbed for selecting one or more array blocks of such a memory array, for selecting one or more word lines [SWL of figure 1] and bit lines [SBL o figure 1] within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks
摘要翻译：描述用于解码图1的可编程的示例性存储器阵列的图[154]和方法，在一些实施例中，图1的可重写无源元件存储单元[101]，其对于极端特别有用具有多于一个存储器平面的致密三维存储器阵列[图12]另外，描述用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择一个或多个字线[图1的SWL]和在所选择的阵列块内的位线[SBL o图1]，用于将数据信息传送到所选择的阵列块内的选定存储单元，并将未选择的偏置条件传送到未选择的阵列块

9. 发明申请

WO2006065523A3 APPARATUS AND METHOD FOR MEMORY OPERATIONS USING ADDRESS-DEPENDENT CONDITIONS 审中-公开
标题翻译：用于使用地址相关条件的存储器操作的装置和方法
公开(公告)号：WO2006065523A3
公开(公告)日：2006-10-05
申请号：PCT/US2005043074
申请日：2005-11-29
申请人： MATRIX SEMICONDUCTOR INC , SO KENNETH K , FASOLI LUCA G , SCHEUERLEIN ROY E
发明人： SO KENNETH K , FASOLI LUCA G , SCHEUERLEIN ROY E
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1677
摘要： An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.
摘要翻译：公开了一种装置，其包括多个字线和字线驱动器，多个位线和位线驱动器以及耦合在各个字线和位线之间的多个存储单元。该装置还包括电路，该电路用于基于存储器单元相对于字线驱动器和位线驱动器中的一者或两者的位置来选择写入和/或读取条件以施加到存储器单元。该装置还可以包括电路，该电路用于基于相对于字线和/或位线驱动器的存储单元位置来选择要并行编程的多个存储单元。

10. 发明申请

WO2004090905A3 THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED BIT LINE MEMORY ARRAY 审中-公开
标题翻译：配有分隔线位线存储器阵列的三维存储器件
公开(公告)号：WO2004090905A3
公开(公告)日：2005-06-02
申请号：PCT/US2004009756
申请日：2004-03-31
申请人： MATRIX SEMICONDUCTOR INC , SCHEUERLEIN ROY E , ILKBAHAR ALPER , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , ILKBAHAR ALPER , FASOLI LUCA G
IPC分类号： G11C7/18 , G11C11/06 , G11C11/4097 , G11C16/04 , G11C17/12 , G11C17/18 , H01L31/0328
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。

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