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1. 发明申请

WO2008016946A2 METHOD AND APPARATUS FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY 审中-公开
标题翻译：用于读取多级被动元件存储单元阵列的方法和装置
公开(公告)号：WO2008016946A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/074899
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy E. , THORP, Tyler J. , FASOLI, Luca G.
发明人： SCHEUERLEIN, Roy E. , THORP, Tyler J. , FASOLI, Luca G.
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C11/5642 , G11C13/004 , G11C13/0069 , G11C16/24 , G11C16/26 , G11C2013/0054 , G11C2013/009 , G11C2211/5634 , G11C2213/77
摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
摘要翻译：四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选地分别映射到数据状态11,01,00和10. LSB和MSB优选地被映射为不同页面的一部分。为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。中间级参考用于读取LSB。当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

2. 发明申请

WO2008016946A3 METHOD AND APPARATUS FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY 审中-公开
标题翻译：用于读取多级被动元件存储单元阵列的方法和装置
公开(公告)号：WO2008016946A3
公开(公告)日：2009-01-08
申请号：PCT/US2007074899
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , THORP TYLER J , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , THORP TYLER J , FASOLI LUCA G
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C11/5642 , G11C13/004 , G11C13/0069 , G11C16/24 , G11C16/26 , G11C2013/0054 , G11C2013/009 , G11C2211/5634 , G11C2213/77
摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
摘要翻译：四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选地分别映射到数据状态11,01,00和10. LSB和MSB优选地被映射为不同页面的一部分。为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。中间级参考用于读取LSB。当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

3. 发明申请

WO2009085075A1 TWO TERMINAL NONVOLATILE MEMORY USING GATE CONTROLLED DIODE ELEMENTS 审中-公开
标题翻译：使用栅极控制二极管元件的两端非易失性存储器
公开(公告)号：WO2009085075A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/012477
申请日：2008-11-05
申请人： SANDISK 3D LLC , THORP, Tyler, J. , SCHEUERLEIN, Roy, E.
发明人： THORP, Tyler, J. , SCHEUERLEIN, Roy, E.
IPC分类号： H01L27/102 , H01L29/861 , H01L29/868 , G11C11/36 , G11C13/02 , G11C16/02 , G11C17/06 , H01L27/06 , H01L27/24 , H01L27/28 , H01L29/739
CPC分类号： H01L27/1021 , G11C13/0004 , G11C13/003 , G11C16/0466 , G11C2213/72 , G11C2213/76 , H01L27/112 , H01L27/2445 , H01L27/2463 , H01L29/1606 , H01L29/739 , H01L29/8613 , H01L29/868 , H01L29/88 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16
摘要： A nonvolatile memory cell (20) includes a gate (36) controlled diode steering element (22) and a resistivity switching element (24).
摘要翻译：非易失性存储单元（20）包括控制二极管控制元件（22）和电阻率开关元件（24）的栅极（36）。

4. 发明申请

WO2008121977A3 LEVEL SHIFTER CIRCUIT INCORPORATING TRANSISTOR SNAP-BACK PROTECTION 审中-公开
标题翻译：水平更换电路并入晶体管反向保护
公开(公告)号：WO2008121977A3
公开(公告)日：2008-12-04
申请号：PCT/US2008058933
申请日：2008-03-31
申请人： SANDISK 3D LLC , THORP TYLER J , FASOLI LUCA G
发明人： THORP TYLER J , FASOLI LUCA G
IPC分类号： H03K19/0185
CPC分类号： H03K3/35613 , H03K17/102 , H03K19/01721
摘要： Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.
摘要翻译：公开了用于电平移位对应于第一电压域的输入信号的电平移位电路，以产生对应于第二高电压域的一对互补输出信号。用于高电压输出节点的放电电路中的反馈敏感器件被保护，而不管输出节点上的负载如何，并且不需要精确的晶体管尺寸作为输出负载的函数。快速响应敏感器件由与敏感器件串联的电压转换器电路保护，以限制敏感器件上的电压，即使在最高输出电压下的高电容输出节点。然后旁路电压移位器电路以提供完全到达下电源轨的输出低电平。

5. 发明申请

WO2008121977A2 LEVEL SHIFTER CIRCUIT INCORPORATING TRANSISTOR SNAP-BACK PROTECTION 审中-公开
标题翻译：包含晶体管反接保护的电平移位电路
公开(公告)号：WO2008121977A2
公开(公告)日：2008-10-09
申请号：PCT/US2008/058933
申请日：2008-03-31
申请人： SANDISK 3D LLC , THORP, Tyler J. , FASOLI, Luca G.
发明人： THORP, Tyler J. , FASOLI, Luca G.
IPC分类号： H03K19/0185
CPC分类号： H03K3/35613 , H03K17/102 , H03K19/01721
摘要： Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.
摘要翻译：公开了用于电平移位对应于第一电压域的输入信号以产生对应于第二较高电压域的一对互补输出信号的电平移位电路。无论输出节点的负载如何，并且不需要精确的晶体管尺寸作为输出负载的函数，保护用于高压输出节点的放电电路中的快速反接敏感器件都受到保护。快速反接敏感器件受到与敏感器件串联的电压转换器电路的保护，以限制敏感器件两端的电压，即使是在其最高输出电压下的高电容输出节点。然后电压转换器电路被旁路以提供完全到达较低电源电压轨的输出低电平。

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