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    • 1. 发明申请
    • A METHOD OF PREPARATION OF AN EPITAXIAL SUBSTRATE
    • 一种外源基质的制备方法
    • WO2004112126A1
    • 2004-12-23
    • PCT/EP2004/005439
    • 2004-05-19
    • S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A.FAURE, Bruce
    • FAURE, Bruce
    • H01L21/78
    • C30B25/183H01L21/76254Y10S117/915
    • The invention relates to a method of preparation of an epitaxial substrate, in particular a GaN, a SiGe, AIN or InN epitaxial substrate. It is the object of the present invention to provide a process of preparation of an epitaxial substrate which further reduces the influence of the substrate while being at the same time economically viable. The object is solved by providing a base substrate, implanting atomic species in the base substrate to create a weak layer like zone, providing an epitaxial stiffening layer on a surface of a base substrate at a first temperature and isolating the stiffening layer at a second higher temperature, in particular together with a sub-layer of the base substrate, from the remainder of the base substrate, whereby the isolated material creates a pseudo substrate on which a homo- or heteroepitaxial layer is provided.
    • 本发明涉及外延衬底,特别是GaN,SiGe,AlN或InN外延衬底的制备方法。 本发明的目的是提供一种外延衬底的制备方法,其进一步降低了衬底的影响,同时在经济上是可行的。 该目的通过提供一种基底衬底来解决,在基底衬底中注入原子物质以产生类似薄层的区域,在第一温度下在基底衬底的表面上提供外延加强层,并在第二高度隔离加强层 温度,特别是与基底衬底的子层一起,与基底衬底的其余部分相结合,从而隔离材料产生伪衬底,在其上提供均一或异质外延层。
    • 2. 发明申请
    • PASSIVATION OF ETCHED SEMICONDUCTOR STRUCTURES
    • WO2010015301A8
    • 2010-02-11
    • PCT/EP2009/004791
    • 2009-07-02
    • S.O.I. TEC SILICON ON ISULATOR TECHNOLOGIESFAURE, BruceGUENARD, Pascal
    • FAURE, BruceGUENARD, Pascal
    • H01L21/762H01L21/324H01L21/20
    • The present invention relates to a method for passivation of a semiconductor structure, comprising the steps providing at least one first material layer; forming at least one second material layer that is to be patterned above the first material layer; forming a diffusion barrier layer between the at least one second material layer and the at least one first material layer thereby forming a multilayer stack and patterning, in particular, etching, the at least one second material layer down to but not completely through the diffusion barrier layer and without exposing portions of the at least one first material layer such that diffusion of material of the at least one first material layer through the diffusion barrier layer during a subsequent heat treatment of the multilayer stack is substantially prevented. The invention also relates to a method for passivation of a semiconductor structure, comprising the steps providing a multilayer stack comprising at least one buried layer formed below a second material layer; patterning, in particular, etching, the surface of the multilayer stack through the second material layer thereby exposing portions of the at least one buried layer and depositing a diffusion barrier layer at least on the exposed portions of the at least one buried layer such that diffusion of material of the at least one buried layer through the diffusion barrier layer during a subsequent heat treatment of the multilayer stack is substantially prevented.