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1. 发明申请

WO2004112126A1 A METHOD OF PREPARATION OF AN EPITAXIAL SUBSTRATE 审中-公开
标题翻译：一种外源基质的制备方法
公开(公告)号：WO2004112126A1
公开(公告)日：2004-12-23
申请号：PCT/EP2004/005439
申请日：2004-05-19
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A. , FAURE, Bruce
发明人： FAURE, Bruce
IPC分类号： H01L21/78
CPC分类号： C30B25/183 , H01L21/76254 , Y10S117/915
摘要： The invention relates to a method of preparation of an epitaxial substrate, in particular a GaN, a SiGe, AIN or InN epitaxial substrate. It is the object of the present invention to provide a process of preparation of an epitaxial substrate which further reduces the influence of the substrate while being at the same time economically viable. The object is solved by providing a base substrate, implanting atomic species in the base substrate to create a weak layer like zone, providing an epitaxial stiffening layer on a surface of a base substrate at a first temperature and isolating the stiffening layer at a second higher temperature, in particular together with a sub-layer of the base substrate, from the remainder of the base substrate, whereby the isolated material creates a pseudo substrate on which a homo- or heteroepitaxial layer is provided.
摘要翻译：本发明涉及外延衬底，特别是GaN，SiGe，AlN或InN外延衬底的制备方法。本发明的目的是提供一种外延衬底的制备方法，其进一步降低了衬底的影响，同时在经济上是可行的。该目的通过提供一种基底衬底来解决，在基底衬底中注入原子物质以产生类似薄层的区域，在第一温度下在基底衬底的表面上提供外延加强层，并在第二高度隔离加强层温度，特别是与基底衬底的子层一起，与基底衬底的其余部分相结合，从而隔离材料产生伪衬底，在其上提供均一或异质外延层。

2. 发明申请

WO2008014079A1 STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES 审中-公开
标题翻译：半导体缓冲器结构中的应变层
公开(公告)号：WO2008014079A1
公开(公告)日：2008-01-31
申请号：PCT/US2007/072252
申请日：2007-06-27
申请人： ASM AMERICA, INC. , S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
发明人： CODY, Nyles, W. , FIGUET, Christophe , KENNARD, Mark
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532
摘要： A semiconductor workpiece including a substrate 10, a relaxed buffer layer 14, 18 including a graded portion formed on the substrate, and at least one strained transitional layer 16 within the graded portion of the relaxed buffer layer 14, 18 and method of manufacturing the same. The at least one strained transitional layer 16 reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer 14, 18 relative to CTE contraction of the substrate 10.
摘要翻译：包括衬底10的半导体工件，包括形成在衬底上的渐变部分的松弛缓冲层14,18以及松弛缓冲层14,18的渐变部分内的至少一个应变过渡层16及其制造方法。至少一个应变过渡层16由于缓冲缓冲层14,18相对于衬底10的CTE收缩的差异热膨胀系数（CTE）收缩而减少了工件弓形的数量。

3. 发明申请

WO2007133358A2 SEMICONDUCTOR BUFFER STRUCTURES 审中-公开
公开(公告)号：WO2007133358A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/008879
申请日：2007-04-09
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES, S.A. , CODY, Nyles, W. , ARENA, Chantel , TOMASINI, Pierre , MAZURE, Carlos
发明人： CODY, Nyles, W. , ARENA, Chantel , TOMASINI, Pierre , MAZURE, Carlos
IPC分类号： C23C16/22 , C23C16/455 , C30B29/02 , C30B25/14
CPC分类号： C23C16/22 , C23C16/24 , C23C16/45523 , C30B25/165 , C30B29/52
摘要： Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.
摘要翻译：通过增强位错滑行，减少厚度梯度缓冲层穿透位错的堆积。在形成渐变的SiGe缓冲层期间，从硅前体和锗前体的SiGe的沉积被中断一次或多次，其中停止向硅衬底的硅前驱体的流动，同时锗前体流向保持底物。

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