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1. 发明申请

WO2010015301A8 PASSIVATION OF ETCHED SEMICONDUCTOR STRUCTURES 审中-公开
公开(公告)号：WO2010015301A8
公开(公告)日：2010-02-11
申请号：PCT/EP2009/004791
申请日：2009-07-02
申请人： S.O.I. TEC SILICON ON ISULATOR TECHNOLOGIES , FAURE, Bruce , GUENARD, Pascal
发明人： FAURE, Bruce , GUENARD, Pascal
IPC分类号： H01L21/762 , H01L21/324 , H01L21/20
摘要： The present invention relates to a method for passivation of a semiconductor structure, comprising the steps providing at least one first material layer; forming at least one second material layer that is to be patterned above the first material layer; forming a diffusion barrier layer between the at least one second material layer and the at least one first material layer thereby forming a multilayer stack and patterning, in particular, etching, the at least one second material layer down to but not completely through the diffusion barrier layer and without exposing portions of the at least one first material layer such that diffusion of material of the at least one first material layer through the diffusion barrier layer during a subsequent heat treatment of the multilayer stack is substantially prevented. The invention also relates to a method for passivation of a semiconductor structure, comprising the steps providing a multilayer stack comprising at least one buried layer formed below a second material layer; patterning, in particular, etching, the surface of the multilayer stack through the second material layer thereby exposing portions of the at least one buried layer and depositing a diffusion barrier layer at least on the exposed portions of the at least one buried layer such that diffusion of material of the at least one buried layer through the diffusion barrier layer during a subsequent heat treatment of the multilayer stack is substantially prevented.

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