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1. 发明申请

WO2009105282A1 MULTIPLE INTERFACE MEMORY WITH SEGMENTED I/O COLUMNS RECONFIGURABLE WITH RESPECT TO THE INTERFACES 审中-公开
标题翻译：具有相邻接口的可重新配置的多个I / O柱的多个接口存储器
公开(公告)号：WO2009105282A1
公开(公告)日：2009-08-27
申请号：PCT/US2009/001160
申请日：2009-02-20
申请人： RAMBUS, INC. , WARE, Frederick, A. , KUCHIBHOTLA, Venu, Madhav
发明人： WARE, Frederick, A. , KUCHIBHOTLA, Venu, Madhav
IPC分类号： G11C7/10
CPC分类号： G11C7/1075
摘要： A memory (102) includes segmented I/O columns to provide access to data storage elements (105) in memory segments via multiple data I/O interfaces. A column segment control (107) in each column I/O path enables access to the data storage elements in a first mode by a first processor interface (108A). In a second mode, the column segment controls are used to partition the array and provide mutually exclusive access to subsets of the array to different interfaces (108A, 108B).
摘要翻译：存储器（102）包括分段的I / O列，以通过多个数据I / O接口提供对存储器段中的数据存储元件（105）的访问。每列I / O路径中的列分段控制（107）使得能够通过第一处理器接口（108A）以第一模式访问数据存储元件。在第二模式中，列分段控件用于对阵列进行分区，并向阵列的子集提供对不同接口（108A，108B）的互斥访问。

2. 发明申请

WO2012125719A2 METHODS AND APPARATUS FOR TESTING INACCESSIBLE INTERFACE CIRCUITS IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于测试半导体器件中不可接受的接口电路的方法和装置
公开(公告)号：WO2012125719A2
公开(公告)日：2012-09-20
申请号：PCT/US2012/029071
申请日：2012-03-14
申请人： RAMBUS INC. , WARE, Frederick, A.
发明人： WARE, Frederick, A.
IPC分类号： G01R31/3183
CPC分类号： G01R31/2882 , G01R31/2607 , G01R31/31726 , G11C29/022 , G11C29/12015 , G11C29/16 , G11C29/50012 , G11C2029/0401 , H03L7/00
摘要： A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.
摘要翻译：半导体IC器件包括用于传送定时信号的定时电路，定时电路被配置为接收第一测试信号并且响应于第一测试信号实现定时信号的延迟，第一测试信号包括第一定时事件。半导体IC器件还包括接口电路，被配置为响应于定时信号传送数据信号，接口电路还被配置为接收第二测试信号并且响应于第二测试信号来实现数据信号的延迟所述第二测试信号包括根据测试标准与所述第一定时事件相关的第二定时事件。

3. 发明申请

WO2010101754A2 MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATION 审中-公开
标题翻译：具有交互控制信息的记忆接口
公开(公告)号：WO2010101754A2
公开(公告)日：2010-09-10
申请号：PCT/US2010/025316
申请日：2010-02-25
申请人： RAMBUS INC. , WARE, Frederick, A.
发明人： WARE, Frederick, A.
IPC分类号： G11C7/10 , G11C7/22 , G11C8/04
CPC分类号： G11C7/1006 , G06F13/1647 , G11C7/1009 , G11C7/1012 , G11C8/04 , Y02D10/14
摘要： A memory system communicates at least partially temporally overlapping write-data sequences associated with independent column write accesses on data links from a memory controller to a memory device via bidirectional links. Each of these write-data sequences may be associated with a different bank set in the memory IC. These bank sets may be micro-threaded so that each bank set is independently addressable and can concurrently perform operations associated with independent commands, including simultaneous column read/write. Furthermore, temporally interleaved data-mask information for the write-data sequences may be communicated from the memory controller to the memory IC via a data-mask link, so that alternate bits in the interleaved data-mask information may correspond to different write sequences.
摘要翻译：存储器系统通过双向链路将与数据链路上的独立列写访问相关联的至少部分时间上重叠的写数据序列从存储器控制器传送到存储器设备。这些写入数据序列中的每一个可以与存储器IC中的不同的存储体组相关联。这些存储体组可以是微线程的，使得每个存储体集可独立地寻址，并且可以同时执行与独立命令相关联的操作，包括同时列读/写。此外，用于写数据序列的时间交织的数据掩码信息可以经由数据掩码链路从存储器控制器传送到存储器IC，使得交错数据掩码信息中的交替位可对应于不同的写序列。

4. 发明申请

WO2008057557A2 MEMORY SYSTEM SUPPORTING NONVOLATILE PHYSICAL MEMORY 审中-公开
标题翻译：支持非易失性物理内存的存储器系统
公开(公告)号：WO2008057557A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/023432
申请日：2007-11-06
申请人： RAMBUS INC. , WARE, Frederick, A. , TSERN, Ely, K.
发明人： WARE, Frederick, A. , TSERN, Ely, K.
CPC分类号： G06F12/0253 , G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0891 , G06F12/1009 , G06F2212/1036 , G06F2212/2022 , G06F2212/60 , G06F2212/7201 , G06F2212/7205 , G06F2212/7211
摘要： A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
摘要翻译：存储器系统包括非易失性物理存储器，例如闪存，其呈现与写入操作不对称关联的磨损机制。易失性存储器的相对较小的缓存减少了写入次数，并且耗损均衡的存储器访问方法均匀地将写入分散在非易失性存储器中。

5. 发明申请

WO2008014189A2 PARTITIONED GAME CONSOLE SYSTEM 审中-公开
标题翻译：分区游戏控制台系统
公开(公告)号：WO2008014189A2
公开(公告)日：2008-01-31
申请号：PCT/US2007/073964
申请日：2007-07-20
申请人： RAMBUS INC. , WARE, Frederick, A. , TSERN, Ely, K.
发明人： WARE, Frederick, A. , TSERN, Ely, K.
IPC分类号： G06F1/20
CPC分类号： A63F13/23 , A63F13/00 , A63F2300/203 , A63F2300/405 , A63F2300/538 , G06F1/20
摘要： The game console system includes a user interface module and a graphics processing module that are remotely situated from one another and solely coupled to one another via one or more communication links. The graphics processing module is positioned within a controlled environment chamber that thermally and acoustically isolates the user interface module from the graphics processing module. The user interface module includes a controller and a console coupled to the controller. The console also is configured to be coupled to a display.
摘要翻译：游戏控制台系统包括用户界面模块和图形处理模块，它们彼此远离地定位并且经由一个或多个通信链路彼此单独耦合。图形处理模块位于受控环境室内，该受控环境室将用户界面模块与图形处理模块热和声学隔离。用户界面模块包括控制器和耦合到控制器的控制台。控制台也被配置为连接到显示器。

6. 发明申请

WO2005072329A3 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 审中-公开
公开(公告)号：WO2005072329A3
公开(公告)日：2005-08-11
申请号：PCT/US2005/002301
申请日：2005-01-25
申请人： RAMBUS, INC. , WARE, Frederick, A. , PEREGO, Richard, E. , HAMPEL, Craig, E.
发明人： WARE, Frederick, A. , PEREGO, Richard, E. , HAMPEL, Craig, E.
IPC分类号： H04B3/00
摘要： A method provides for execution of calibration cycles during normal operation of the communication channel (1002). A calibration cycle includes de-coupling the normal data source (1010) from the transmitter (1003) and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver (1004) on the second component (1001). A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel (1002). For bidirectional links, calibration cycles are executed which include the step of storing received calibration pattern on the second component (1001), and retransmitting such calibration back to the first component (1000) for use in adjusting parameter of the channel at first component (1000).

7. 发明申请

WO2013015893A1 MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION 审中-公开
标题翻译：记忆与诽谤的活动
公开(公告)号：WO2013015893A1
公开(公告)日：2013-01-31
申请号：PCT/US2012/041758
申请日：2012-06-08
申请人： RAMBUS INC. , HARRIS, James, Edward , VOGELSANG, Thomas , WARE, Frederick, A. , SHAEFFER, Ian, P.
发明人： HARRIS, James, Edward , VOGELSANG, Thomas , WARE, Frederick, A. , SHAEFFER, Ian, P.
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1039 , G11C5/025 , G11C7/06 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
摘要翻译：存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。此外，代替激活响应于行命令的子代码，延迟激活操作被延迟，直到接收到指定要执行的列操作的列命令和被激活的子代。

8. 发明申请

WO2010098901A2 SYNTHETIC PULSE GENERATOR FOR REDUCING SUPPLY NOISE 审中-公开
标题翻译：降低供电噪声的综合脉冲发生器
公开(公告)号：WO2010098901A2
公开(公告)日：2010-09-02
申请号：PCT/US2010/021024
申请日：2010-01-14
申请人： RAMBUS INC. , WARE, Frederick, A.
发明人： WARE, Frederick, A.
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H03K19/017581 , H03K19/017509 , H04L25/0272
摘要： A source-terminated transmitter conveys digital signals over a short channel as a voltage signal that transitions between levels for each symbol transition. The transmitter produces each transition by issuing a charge pulse onto the channel, and thus creates a series of charge pulses. The number of charge pulses per unit time is proportional to the transition density of the signal, as no charge pulse is required between like symbols. The supply current used to deliver the pulses is therefore dependent upon the data pattern. This data dependency can induce supply fluctuations, which can in turn cause errors and otherwise reduce performance. The transmitter issues a synthetic charge pulse for each adjacent pair of like symbols to reduce the data dependency of the supply current. The synthetic pulses can be scaled to match the charge required for symbol transitions on a given channel.
摘要翻译：源终端发射机通过短信道传送数字信号作为在每个符号转换的电平之间转换的电压信号。发射器通过在通道上发出充电脉冲产生每个转换，从而产生一系列电荷脉冲。每单位时间的充电脉冲数量与信号的转换密度成正比，因为在相同符号之间不需要电荷脉冲。因此用于传送脉冲的电源电流取决于数据模式。这种数据依赖性会导致供应波动，进而导致错误并降低性能。发射机针对每个相邻的一对相似符号发出合成电荷脉冲，以降低电源电流的数据依赖性。合成脉冲可以缩放以匹配给定通道上符号转换所需的电荷。

9. 发明申请

WO2010085405A1 MAINTENANCE OPERATIONS IN A DRAM 审中-公开
标题翻译： DRAM中的维护操作
公开(公告)号：WO2010085405A1
公开(公告)日：2010-07-29
申请号：PCT/US2010/020934
申请日：2010-01-13
申请人： RAMBUS INC. , WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W.
IPC分类号： G06F13/16 , G11C11/406
CPC分类号： G06F3/0619 , G06F3/0629 , G06F3/0659 , G06F3/0673 , G06F13/1636 , G06F13/1689 , G06Q10/00 , G06Q20/00 , G11C7/02 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C2211/4061
摘要： A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.
摘要翻译：一种系统包括存储器控制器和具有命令接口和多个存储器组的存储器件，每个存储体具有多行存储器单元。存储器控制器向存储器件发送自动刷新命令。响应于自动刷新命令，在第一时间间隔期间，存储器件执行刷新操作以刷新存储器单元，并且存储器件的命令接口在第一时间间隔的持续时间内被置于校准模式。同时，在第一时间间隔的至少一部分期间，存储器控制器执行存储器件的命令接口的校准。自动刷新命令可以指定要刷新存储器件的存储体的顺序，使得存储器件以指定的存储体顺序顺序刷新多个存储体中的相应行。

10. 发明申请

WO2010080176A1 MESOCHRONOUS SIGNALING SYSTEM WITH MULTIPLE POWER MODES 审中-公开
标题翻译：具有多种功率模式的MESOCHRONOUS信号系统
公开(公告)号：WO2010080176A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050044
申请日：2009-07-09
申请人： RAMBUS INC. , WARE, Frederick, A. , POULTON, John, W. , PALMER, Robert, E.
发明人： WARE, Frederick, A. , POULTON, John, W. , PALMER, Robert, E.
IPC分类号： G11C11/407 , G11C8/00 , H03L7/081
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以使得能够以源同步定时参考不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

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