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1. 发明申请

WO2011025557A1 FORWARDING SIGNAL SUPPLY VOLTAGE IN DATA TRANSMISSION SYSTEM 审中-公开
标题翻译：数据传输系统中的前向信号供电电压
公开(公告)号：WO2011025557A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/029252
申请日：2010-03-30
申请人： RAMBUS INC. , BEST, Scott, C. , POULTON, John, W.
发明人： BEST, Scott, C. , POULTON, John, W.
IPC分类号： G11C5/14 , G06F13/40 , G11C7/10
CPC分类号： G11C5/144 , G06F11/0727 , G06F11/076 , G06F11/0793 , G06F13/4072 , G11C5/145 , H04L1/203 , H04L25/0264 , H04L25/08
摘要： In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.
摘要翻译：在数据传输系统中，在第一电路中生成用于产生要发送的信号的信令电压的一个或多个信号电源电压，并从第一电路转发到第二电路。第二电路可以使用转发的信号电源电压来产生要从第二电路传输回第一电路的另一个信号，从而避免在第二电路中单独产生信号电源电压的需要。第一电路还可以基于从第二电路传输回第一电路的信号来调整信号电源电压。数据传输系统可以使用单端信令系统，其中信令电压参考作为由第一电路和第二电路共享的诸如地的电源电压的参考电压。

2. 发明申请

WO2010111619A3 VOLTAGE MODE TRANSMITTER EQUALIZER 审中-公开
标题翻译：电压模式发射机均衡器
公开(公告)号：WO2010111619A3
公开(公告)日：2011-01-27
申请号：PCT/US2010028871
申请日：2010-03-26
申请人： RAMBUS INC , DETTLOFF WAYNE D , POULTON JOHN W , WILSON JOHN M
发明人： DETTLOFF WAYNE D , POULTON JOHN W , WILSON JOHN M
IPC分类号： H04L25/03 , H03H17/00 , H03H21/00 , H03K19/0175 , H04L25/02
CPC分类号： H04L25/03343 , H04L25/0272 , H04L25/0278 , H04L25/03885
摘要： A voltage mode transmitter equalizer has high efficiencies, yet consumes substantially constant supply current from the power supply and provides constant back-match impedance. The voltage mode transmitter equalizer is configured such that the output voltage of the signal to be output on a pair of transmission lines can be controlled according to the input data, but its return impedance is substantially matched to the differential impedance of the transmission lines and it draws substantially constant supply current from the power supply regardless of the output voltage of the signal. Further, an equalizer for a voltage-mode transmitter provides fine-granularity equalization settings by employing a variable pull-up conductance and a variable pull-down conductance. Conductance is varied by selectively enabling a plurality of conductance channels, at least some of which have resistance values that are distinct from one another.
摘要翻译：电压模式发射机均衡器具有高效率，但是从电源消耗基本恒定的电源电流并提供恒定的反匹配阻抗。电压模式发射机均衡器被配置为使得可以根据输入数据来控制要在一对传输线上输出的信号的输出电压，但是其返回阻抗基本上与传输线的差分阻抗匹配，并且它无论信号的输出电压如何，都能从电源中抽取大致恒定的电源电流。此外，用于电压模式发射机的均衡器通过采用可变上拉电导和可变下拉电导来提供细粒度均衡设置。通过选择性地启用多个电导通道来改变电导，其中至少一些导电通道具有彼此不同的电阻值。

3. 发明申请

WO2010080172A1 CLOCK-FORWARDING LOW-POWER SIGNALING SYSTEM 审中-公开
标题翻译：时钟转换低功率信号系统
公开(公告)号：WO2010080172A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050016
申请日：2009-07-09
申请人： RAMBUS INC. , WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W.
IPC分类号： G11C7/22 , G11C8/00 , G11C5/14
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以使得能够以源同步定时参考不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

4. 发明申请

WO2007133872A2 SIGNALING SYSTEM WITH LOW-POWER AUTOMATIC GAIN CONTROL 审中-公开
标题翻译：具有低功率自动增益控制的信号系统
公开(公告)号：WO2007133872A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/066511
申请日：2007-04-12
申请人： RAMBUS INC. , DALLY, William , POULTON, John W.
发明人： DALLY, William , POULTON, John W.
CPC分类号： H03G3/3036 , H03G3/3052 , H03K2005/00039
摘要： An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within the memory circuit. The update circuit generates an updated gain control value based on the amplified signal during the first interval, and outputs the updated gain control value to the memory circuit to be stored therein at a conclusion of the first interval.
摘要翻译：集成电路装置包括可变增益放大器，存储电路和增益控制更新电路。可变增益放大器至少在第一间隔期间内在存储器电路内产生具有根据增益控制值的幅度的放大信号。更新电路基于第一间隔期间的放大信号产生更新的增益控制值，并且在第一间隔的结论处将更新的增益控制值输出到要存储在其中的存储器电路。

5. 发明申请

WO2010080173A1 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 审中-公开
标题翻译：具有时钟停止低功耗模式的MESOCHRONOUS信号系统
公开(公告)号：WO2010080173A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050020
申请日：2009-07-09
申请人： RAMBUS INC. , WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G06F1/04 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

6. 发明申请

WO2010039365A1 SIGNAL CALIBRATION METHODS AND APPARATUSES 审中-公开
标题翻译：信号校准方法和装置
公开(公告)号：WO2010039365A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/055106
申请日：2009-08-27
申请人： RAMBUS INC. , WARE, Frederick , NAVID, Reza , POULTON, John, W.
发明人： WARE, Frederick , NAVID, Reza , POULTON, John, W.
IPC分类号： H03L7/00 , H04L7/00
CPC分类号： H03L7/00
摘要： In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal and low speed clock signals associated with different phases of the clock tree. In some aspects, the desired phase of a clock tree may be maintained by detecting framing offsets that occur through the use of the clock tree.
摘要翻译：在信号校准方案中，在一组信号之间保持期望的相位关系。例如，在一些方面，可以通过检测低速参考时钟信号和与时钟树的不同相位相关联的低速时钟信号之间的相位差来维持从高速参考时钟信号产生的时钟树的期望相位。在某些方面，通过检测通过使用时钟树发生的成帧偏移，可以维持时钟树的所需相位。

7. 发明申请

WO2008100494A4 DIFFERENTIAL RECEIVER WITH COMMON-GATE INPUT STAGE 审中-公开
标题翻译：差分接收器与通用输入级
公开(公告)号：WO2008100494A4
公开(公告)日：2009-02-12
申请号：PCT/US2008001826
申请日：2008-02-11
申请人： RAMBUS INC , PALMER ROBERT E , POULTON JOHN W
发明人： PALMER ROBERT E , POULTON JOHN W
IPC分类号： H04L25/02 , H03F3/45
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： A low-voltage differential communication system includes a low- and programmable-swing voltage-mode transmitter that delivers a low- voltage differential signal to a receiver via differential channel. The receiver employs two input transistors, each in a common-gate configuration, to recover the low- voltage differential signal. A current source in the receiver biases the input transistors such that their source voltages are nominally biased at the common- mode voltage of the differential signal, and their gate-source voltages remain essentially constant with common-mode-voltage fluctuations.
摘要翻译：低压差分通信系统包括一个低和可编程摆幅电压模式发送器，通过差分通道向接收器传送低电压差分信号。接收机采用两个输入晶体管，每个输入晶体管以共栅极配置，以恢复低电压差分信号。接收器中的电流源偏置输入晶体管，使得它们的源极电压在标称偏置在差分信号的共模电压上，并且它们的栅源电压在共模电压波动下保持基本恒定。

8. 发明申请

WO2008100523A3 LOW-POWER CLOCK GENERATION AND DISTRIBUTION CIRCUITRY 审中-公开
公开(公告)号：WO2008100523A3
公开(公告)日：2008-08-21
申请号：PCT/US2008/001869
申请日：2008-02-12
申请人： RAMBUS INC. , POULTON, John, W. , PALMER, Robert, E. , FULLER, Andrew, M.
发明人： POULTON, John, W. , PALMER, Robert, E. , FULLER, Andrew, M.
IPC分类号： G06F1/10 , G06F1/32
摘要： A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.

9. 发明申请

WO2007133872A3 SIGNALING SYSTEM WITH LOW-POWER AUTOMATIC GAIN CONTROL 审中-公开
标题翻译：具有低功率自动增益控制的信号系统
公开(公告)号：WO2007133872A3
公开(公告)日：2008-04-10
申请号：PCT/US2007066511
申请日：2007-04-12
申请人： RAMBUS INC , DALLY WILLIAM , POULTON JOHN W
发明人： DALLY WILLIAM , POULTON JOHN W
IPC分类号： H03G3/30
CPC分类号： H03G3/3036 , H03G3/3052 , H03K2005/00039
摘要： An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within the memory circuit. The update circuit generates an updated gain control value based on the amplified signal during the first interval, and outputs the updated gain control value to the memory circuit to be stored therein at a conclusion of the first interval.
摘要翻译：集成电路装置包括可变增益放大器，存储电路和增益控制更新电路。可变增益放大器产生具有根据增益控制值的幅度的放大信号，所述增益控制值至少在第一间隔期间被存储在存储器电路内。更新电路基于第一间隔期间的放大信号产生更新的增益控制值，并且在第一间隔的结论处将更新的增益控制值输出到要存储在其中的存储器电路。

10. 发明申请

WO2006078730A3 COMMUNICATION SYSTEM WITH LOW POWER, DC-BALANCED SERIAL LINK 审中-公开
标题翻译：具有低功耗，直流平衡串行链路的通信系统
公开(公告)号：WO2006078730A3
公开(公告)日：2006-11-16
申请号：PCT/US2006001754
申请日：2006-01-19
申请人： RAMBUS INC , DALLY WILLIAM J , POULTON JOHN W
发明人： DALLY WILLIAM J , POULTON JOHN W
IPC分类号： H04B3/00 , H04L25/34 , H04L27/22
CPC分类号： H04L25/4904 , H03K3/356139 , H04L25/0284 , H04L25/0296 , H04L25/085
摘要： A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, to produce output representing the codewords. A sense circuit produces an output data stream.
摘要翻译：数据通信系统包括第一和第二集成电路之间的传输线。第一集成电路上的编码器对输入数据流进行编码以产生码字序列，其中该序列中的码字是表示输入数据流中的数据的一组码字的成员，并且该组的成员基本上是DC平衡的，如曼彻斯特编码符号集。第二集成电路上的积分电路通过在特定符号单元内对具有正极性的第一间隔进行积分并在具体符号单元内对具有负极性的第二间隔进行积分来积分代码字以产生表示代码字的输出。感测电路产生输出数据流。

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