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1. 发明申请

WO2009111208A1 MULTIPLE TRANSMITTER SYSTEM AND METHOD 审中-公开
标题翻译：多传输系统和方法
公开(公告)号：WO2009111208A1
公开(公告)日：2009-09-11
申请号：PCT/US2009/034943
申请日：2009-02-24
申请人： QUALCOMM INCORPORATED , LEE, Chulkyu , DAVIERWALLA, Anosh B. , WILEY, George A.
发明人： LEE, Chulkyu , DAVIERWALLA, Anosh B. , WILEY, George A.
IPC分类号： H04L5/20 , H04L25/02
CPC分类号： H04L25/0272 , H04L25/49
摘要： Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.
摘要翻译：公开了数据传输的系统和方法。在一个实施例中，选择性地激活至少两个发射机，并且至少一个发射机在串行接口处被去激活，以经由至少两条不同的线路传输数据。

2. 发明申请

WO2009003068A1 LEVEL SHIFTER HAVING LOW DUTY CYCLE DISTORTION 审中-公开
标题翻译：具有低占空比的水平变换器
公开(公告)号：WO2009003068A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/068247
申请日：2008-06-25
申请人： QUALCOMM Incorporated , LEE, Chulkyu
发明人： LEE, Chulkyu
IPC分类号： H03K3/356
CPC分类号： H03K3/356113
摘要： A level shifter (100) includes an inverting circuit (104), a cross-coupled level shifting latch (102), and a SR logic gate latch (103). The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal (IND) onto a first input of the level shifting latch (112) and supplies an inverted version of the input signal (INB) onto a second input of the level shifting latch (113). A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.
摘要翻译：电平移位器（100）包括反相电路（104），交叉耦合电平移位锁存器（102）和SR逻辑门锁存器（103）。电平移位锁存器的第一和第二输出耦合到SR锁存器的组（S）和复位（R）输入端。由第一电源电压VDDL供电的反相电路将输入信号（IND）的非反相版本提供到电平移位锁存器（112）的第一输入端，并将输入信号（INB）的反相版本提供到电平移位锁存器（113）的第二输入端。输入信号的低电平到高电平跳变使SR锁存器复位，而高电平至低电平转换则设置SR锁存器。电平转换器的占空比失真偏移在电压，过程和温度转角上小于50皮秒，电平转换器的电源电压裕度大于VDDL额定值的四分之一。

3. 发明申请

WO2015176295A1 FEED-FORWARD BIAS CIRCUIT 审中-公开
标题翻译：进给前进偏置电路
公开(公告)号：WO2015176295A1
公开(公告)日：2015-11-26
申请号：PCT/CN2014/078223
申请日：2014-05-23
申请人： QUALCOMM INCORPORATED , SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
发明人： SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
IPC分类号： H02M3/07
CPC分类号： H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
摘要： A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit.In some aspects,the feed- forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions.In some implementations,the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.
摘要翻译：前馈偏置电路偏置另一电路的晶体管的体偏置端子，以补偿另一电路中的PVT变化。在一些方面，前馈偏置电路通过使能产生不同偏置来补偿电路中的晶体管工艺角在一些实施方案中，前馈偏置电路用于偏置延迟电路，使得延迟电路在不同的PVT条件下表现出相对恒定的延迟特性。

4. 发明申请

WO2011150172A1 METHOD AND APPARATUS TO SERIALIZE PARALLEL DATA INPUT VALUES 审中-公开
标题翻译：串并行数据输入值的方法和装置
公开(公告)号：WO2011150172A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/038086
申请日：2011-05-26
申请人： QUALCOMM INCORPORATED , LEE, Chulkyu , DANG, Harry, H. , DIXIT, Abhay, S.
发明人： LEE, Chulkyu , DANG, Harry, H. , DIXIT, Abhay, S.
IPC分类号： H03M9/00
CPC分类号： H03K19/096 , G06F17/50 , H03K19/20 , H03M9/00
摘要： A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a selection circuit, where the input tier includes multiple combinatorial gate multiplexers. The method further includes selecting an output value at an output tier of the selection circuit, where the output tier includes at least one combinatorial gate multiplexer.
摘要翻译：公开了串行化并行数据输入值的方法和装置。在特定实施例中，串行化并行数据输入值的方法包括在选择电路的输入层处并行接收多个数据输入值，其中输入层包括多个组合门多路复用器。该方法还包括在选择电路的输出层选择输出值，其中输出层包括至少一个组合门多路复用器。

5. 发明申请

WO2015176244A1 SERIALIZER AND DESERIALIZER FOR ODD RATIO PARALLEL DATA BUS 审中-公开
标题翻译：用于ODD比例并行数据总线的SERIALIZER和DESERIALIZER
公开(公告)号：WO2015176244A1
公开(公告)日：2015-11-26
申请号：PCT/CN2014/077979
申请日：2014-05-21
申请人： QUALCOMM INCORPORATED , ZHANG, Le , SU, Wenjun , LEE, Chulkyu
发明人： ZHANG, Le , SU, Wenjun , LEE, Chulkyu
IPC分类号： H03M9/00
CPC分类号： G06F1/324 , G06F1/08 , G06F13/4022 , G06F13/4282 , G11C19/28 , H03M9/00 , Y02D10/14 , Y02D10/151
摘要： Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.
摘要翻译：公开了用于奇数比并行数据总线的串行器和解串器。在一个实施例中，以奇数个并行数据位操作的串行器和解串行器与半速率时钟一起工作，以全时钟速率提供串行数据流。通过提供半速率时钟，集成了串行器的集成电路的功率和面积是保守的。此外，通过提供7：1串行器，该总线现在与MIPI C-PHY标准兼容。

6. 发明申请

WO2017156241A1 INTELLIGENT EQUALIZATION FOR A THREE-TRANSMITTER MULTI-PHASE SYSTEM 审中-公开
标题翻译：一个三发多相系统的智能均衡
公开(公告)号：WO2017156241A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/021531
申请日：2017-03-09
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , CHOU, Shih-Wei , WILEY, George
IPC分类号： H04L25/49 , H04L25/03 , H04L25/02 , H03K5/153 , H04L25/14
摘要： An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.
摘要翻译：为三发射机系统提供智能均衡技术，其中中级转换被选择性地强调和去强调以节省功率并减少数据抖动。

7. 发明申请

WO2017039985A1 MULTIPHASE CLOCK DATA RECOVERY FOR A 3-PHASE INTERFACE 审中-公开
标题翻译：用于三相接口的多相时钟数据恢复
公开(公告)号：WO2017039985A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/046211
申请日：2016-08-09
申请人： QUALCOMM INCORPORATED
发明人： DUAN, Ying , LEE, Chulkyu , CHOU, Shih-Wei , DANG, Harry , KWON, Ohjoon
IPC分类号： H04L7/033 , H04L25/49
CPC分类号： H03L7/0807 , H03L7/0812 , H04L7/0037 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L7/04 , H04L25/4917
摘要： Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of data communication includes configuring a clock recovery circuit to provide a first clock signal that includes a pulse for each symbol transmitted on the interface, where symbols are transmitted on the interface at a first frequency, adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more that half the first frequency, where the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols, configuring a clock generation circuit to provide a second clock signal, and capturing symbols from the interface using the first clock signal and the second clock signal.
摘要翻译：公开了通过多线，多相接口进行数据通信的方法，装置和系统。一种数据通信方法包括配置时钟恢复电路以提供第一时钟信号，该第一时钟信号包括在接口上发送的每个符号的脉冲，其中符号以第一频率在接口上发送，调整时钟恢复电路的环路延迟以修改第一时钟以具有不超过第一频率的第二频率的第二频率，其中时钟恢复电路在第一时钟信号中产生用于整数符号中的第一个的脉冲，并且抑制其他符号中的其他符号的脉冲产生整数个符号，配置时钟发生电路以提供第二时钟信号，以及使用第一时钟信号和第二时钟信号从接口捕获符号。

8. 发明申请

WO2017019223A1 TIME BASED EQUALIZATION FOR A C-PHY 3-PHASE TRANSMITTER 审中-公开
标题翻译：基于时间均衡的C-PHY三相发射机
公开(公告)号：WO2017019223A1
公开(公告)日：2017-02-02
申请号：PCT/US2016/039667
申请日：2016-06-27
申请人： QUALCOMM INCORPORATED
发明人： SEJPAL, Dhaval , LEE, Chulkyu , WILEY, George Alan
IPC分类号： H04L25/02 , H04L7/00 , H04L25/49 , H04L7/033 , H04L25/14
CPC分类号： H04B3/54 , H04B3/462 , H04L7/0087 , H04L7/033 , H04L25/0286 , H04L25/14 , H04L25/4917
摘要： A method, an apparatus, and a computer program product for data communication over a multi-wire, multi-phase interface are provided. The method may include providing a sequence of symbols to be transmitted on a 3-wire interface, each symbol in the sequence of symbols defining one of three voltage states for each wire of the 3-wire interface, driving all wires of the 3-wire interface to a common voltage state during a transition from a first transmitted symbol to a second transmitted symbol, driving each wire of the 3-wire interface in accordance with the second transmitted symbol after a predetermined delay. Each wire may be in a different voltage state from the other wires of the 3-wire interface during transmission of the each symbol. The common voltage state may lie between two of the three voltage states.
摘要翻译：提供了一种用于通过多线，多相接口进行数据通信的方法，装置和计算机程序产品。该方法可以包括提供要在3线接口上发送的符号序列，符号序列中的每个符号定义3线接口的每根线的三种电压状态之一，驱动3线的所有线在从第一传输符号到第二传输符号的转变期间接合到公共电压状态，在预定延迟之后根据第二传输符号驱动3线接口的每条线。在每个符号的传输期间，每根导线可能处于与3线接口的其它线不同的电压状态。公共电压状态可以位于三个电压状态中的两个之间。

9. 发明申请

WO2015108847A1 ANALOG BEHAVIOR MODELING FOR 3-PHASE SIGNALING 审中-公开
标题翻译：用于三相信号的模拟行为建模
公开(公告)号：WO2015108847A1
公开(公告)日：2015-07-23
申请号：PCT/US2015/011142
申请日：2015-01-13
申请人： QUALCOMM INCORPORATED
发明人： LI, Xiang , MIDHA, Nakul , RADHAKRISHNAN, Varun , LEE, Chulkyu
IPC分类号： H04L25/02 , G01R31/28 , H04B3/46 , H04L25/49
CPC分类号： H04M1/0266 , G01R31/2848 , H04B17/00 , H04L25/0272 , H04L25/4917
摘要： System, methods and apparatus are described that model analog behavior in a multi-wire, multi-phase communications link. A digital signal representative of a physical connection in a communications link and a virtual signal characterizing a three-phase signal transmitted over the physical connection are generated. The virtual signal may be configured to model one or more analog characteristics of the physical connection. The analog characteristics may include voltage states defining the three-phase signal. The analog characteristics of the physical connection include at least three voltage states corresponding to signaling states of the three-phase signal.
摘要翻译：描述了在多线，多相通信链路中模拟模拟行为的系统，方法和装置。生成表示通信链路中的物理连接的数字信号和表征通过物理连接发送的三相信号的虚拟信号。虚拟信号可以被配置为建模物理连接的一个或多个模拟特性。模拟特性可以包括定义三相信号的电压状态。物理连接的模拟特性包括对应于三相信号的信令状态的至少三个电压状态。

10. 发明申请

WO2015054297A1 EYE PATTERN TRIGGERING BASED ON SYMBOL TRANSITION 审中-公开
标题翻译：基于符号转换的眼睛图案触发
公开(公告)号：WO2015054297A1
公开(公告)日：2015-04-16
申请号：PCT/US2014/059548
申请日：2014-10-07
申请人： QUALCOMM INCORPORATED
发明人： WILEY, George Alan , LEE, Chulkyu
IPC分类号： H04L1/24 , H04L1/20
CPC分类号： H04L7/042 , H04L1/205 , H04L1/206 , H04L1/247 , H04L5/20 , H04L25/0272 , H04L25/0282 , H04L25/0294 , H04L25/0298 , H04L25/4917
摘要： System, methods and apparatus are described that facilitate tests and measurements related to multi-wire, multi-phase communications links. Information is transmitted in N-phase polarity encoded symbols and an eye pattern corresponding to the symbols is generated such that the symbols are aligned with a trigger for each symbol that corresponds to a clock edge used to sample the symbols. The eye pattern may be used to determine sufficiency of setup times in the communication links and other such characteristics defining a communications channel capabilities.
摘要翻译：描述了便于与多线，多相通信链路相关的测试和测量的系统，方法和装置。信息以N相极性编码的符号发送，并且生成与符号相对应的眼图，使得符号与对应于用于采样符号的时钟边缘的每个符号的触发对齐。眼图可以用于确定通信链路中的建立时间的充分性以及定义通信信道能力的其它这样的特性。

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