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1. 发明申请

WO2009111208A1 MULTIPLE TRANSMITTER SYSTEM AND METHOD 审中-公开
标题翻译：多传输系统和方法
公开(公告)号：WO2009111208A1
公开(公告)日：2009-09-11
申请号：PCT/US2009/034943
申请日：2009-02-24
申请人： QUALCOMM INCORPORATED , LEE, Chulkyu , DAVIERWALLA, Anosh B. , WILEY, George A.
发明人： LEE, Chulkyu , DAVIERWALLA, Anosh B. , WILEY, George A.
IPC分类号： H04L5/20 , H04L25/02
CPC分类号： H04L25/0272 , H04L25/49
摘要： Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.
摘要翻译：公开了数据传输的系统和方法。在一个实施例中，选择性地激活至少两个发射机，并且至少一个发射机在串行接口处被去激活，以经由至少两条不同的线路传输数据。

2. 发明申请

WO2009003068A1 LEVEL SHIFTER HAVING LOW DUTY CYCLE DISTORTION 审中-公开
标题翻译：具有低占空比的水平变换器
公开(公告)号：WO2009003068A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/068247
申请日：2008-06-25
申请人： QUALCOMM Incorporated , LEE, Chulkyu
发明人： LEE, Chulkyu
IPC分类号： H03K3/356
CPC分类号： H03K3/356113
摘要： A level shifter (100) includes an inverting circuit (104), a cross-coupled level shifting latch (102), and a SR logic gate latch (103). The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal (IND) onto a first input of the level shifting latch (112) and supplies an inverted version of the input signal (INB) onto a second input of the level shifting latch (113). A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.
摘要翻译：电平移位器（100）包括反相电路（104），交叉耦合电平移位锁存器（102）和SR逻辑门锁存器（103）。电平移位锁存器的第一和第二输出耦合到SR锁存器的组（S）和复位（R）输入端。由第一电源电压VDDL供电的反相电路将输入信号（IND）的非反相版本提供到电平移位锁存器（112）的第一输入端，并将输入信号（INB）的反相版本提供到电平移位锁存器（113）的第二输入端。输入信号的低电平到高电平跳变使SR锁存器复位，而高电平至低电平转换则设置SR锁存器。电平转换器的占空比失真偏移在电压，过程和温度转角上小于50皮秒，电平转换器的电源电压裕度大于VDDL额定值的四分之一。

3. 发明申请

WO2015176295A1 FEED-FORWARD BIAS CIRCUIT 审中-公开
标题翻译：进给前进偏置电路
公开(公告)号：WO2015176295A1
公开(公告)日：2015-11-26
申请号：PCT/CN2014/078223
申请日：2014-05-23
申请人： QUALCOMM INCORPORATED , SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
发明人： SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
IPC分类号： H02M3/07
CPC分类号： H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
摘要： A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit.In some aspects,the feed- forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions.In some implementations,the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.
摘要翻译：前馈偏置电路偏置另一电路的晶体管的体偏置端子，以补偿另一电路中的PVT变化。在一些方面，前馈偏置电路通过使能产生不同偏置来补偿电路中的晶体管工艺角在一些实施方案中，前馈偏置电路用于偏置延迟电路，使得延迟电路在不同的PVT条件下表现出相对恒定的延迟特性。

4. 发明申请

WO2011150172A1 METHOD AND APPARATUS TO SERIALIZE PARALLEL DATA INPUT VALUES 审中-公开
标题翻译：串并行数据输入值的方法和装置
公开(公告)号：WO2011150172A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/038086
申请日：2011-05-26
申请人： QUALCOMM INCORPORATED , LEE, Chulkyu , DANG, Harry, H. , DIXIT, Abhay, S.
发明人： LEE, Chulkyu , DANG, Harry, H. , DIXIT, Abhay, S.
IPC分类号： H03M9/00
CPC分类号： H03K19/096 , G06F17/50 , H03K19/20 , H03M9/00
摘要： A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a selection circuit, where the input tier includes multiple combinatorial gate multiplexers. The method further includes selecting an output value at an output tier of the selection circuit, where the output tier includes at least one combinatorial gate multiplexer.
摘要翻译：公开了串行化并行数据输入值的方法和装置。在特定实施例中，串行化并行数据输入值的方法包括在选择电路的输入层处并行接收多个数据输入值，其中输入层包括多个组合门多路复用器。该方法还包括在选择电路的输出层选择输出值，其中输出层包括至少一个组合门多路复用器。

5. 发明申请

WO2015176244A1 SERIALIZER AND DESERIALIZER FOR ODD RATIO PARALLEL DATA BUS 审中-公开
标题翻译：用于ODD比例并行数据总线的SERIALIZER和DESERIALIZER
公开(公告)号：WO2015176244A1
公开(公告)日：2015-11-26
申请号：PCT/CN2014/077979
申请日：2014-05-21
申请人： QUALCOMM INCORPORATED , ZHANG, Le , SU, Wenjun , LEE, Chulkyu
发明人： ZHANG, Le , SU, Wenjun , LEE, Chulkyu
IPC分类号： H03M9/00
CPC分类号： G06F1/324 , G06F1/08 , G06F13/4022 , G06F13/4282 , G11C19/28 , H03M9/00 , Y02D10/14 , Y02D10/151
摘要： Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.
摘要翻译：公开了用于奇数比并行数据总线的串行器和解串器。在一个实施例中，以奇数个并行数据位操作的串行器和解串行器与半速率时钟一起工作，以全时钟速率提供串行数据流。通过提供半速率时钟，集成了串行器的集成电路的功率和面积是保守的。此外，通过提供7：1串行器，该总线现在与MIPI C-PHY标准兼容。

6. 发明申请

WO2009158541A1 LOW POWER DESERIALIZER AND DEMULTIPLEXING METHOD 审中-公开
标题翻译：低功耗解决方案和解复用方法
公开(公告)号：WO2009158541A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048720
申请日：2009-06-25
申请人： QUALCOMM INCORPORATED , LEE, ChulKyu , WILEY, George, Alan
发明人： LEE, ChulKyu , WILEY, George, Alan
IPC分类号： H03M9/00
CPC分类号： H04Q11/04 , H03M9/00
摘要： A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit streams. The first and second bit streams are respectively serially shifted along a first plurality of shift registers and a second plurality of shift registers. A first portion of the first bit stream in the first plurality of shift registers is selected and a second portion of the second bit stream in the second plurality of shift registers is also selected. A parallel group of data in a parallel data stream is formed from the first and second portions.
摘要翻译：解串器电路和方法根据并行分组将串行比特流转换成并行比特流。解串器和方法包括将串行数据流交替解复用为第一和第二位流。第一和第二比特流分别沿着第一多个移位寄存器和第二多个移位寄存器串行移位。选择第一多个移位寄存器中的第一比特流的第一部分，并且还选择第二多个移位寄存器中的第二比特流的第二部分。并行数据流中的并行数据组由第一和第二部分形成。

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