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1. 发明申请

WO2015176295A1 FEED-FORWARD BIAS CIRCUIT 审中-公开
标题翻译：进给前进偏置电路
公开(公告)号：WO2015176295A1
公开(公告)日：2015-11-26
申请号：PCT/CN2014/078223
申请日：2014-05-23
申请人： QUALCOMM INCORPORATED , SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
发明人： SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
IPC分类号： H02M3/07
CPC分类号： H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
摘要： A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit.In some aspects,the feed- forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions.In some implementations,the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.
摘要翻译：前馈偏置电路偏置另一电路的晶体管的体偏置端子，以补偿另一电路中的PVT变化。在一些方面，前馈偏置电路通过使能产生不同偏置来补偿电路中的晶体管工艺角在一些实施方案中，前馈偏置电路用于偏置延迟电路，使得延迟电路在不同的PVT条件下表现出相对恒定的延迟特性。

2. 发明申请

WO2015176244A1 SERIALIZER AND DESERIALIZER FOR ODD RATIO PARALLEL DATA BUS 审中-公开
标题翻译：用于ODD比例并行数据总线的SERIALIZER和DESERIALIZER
公开(公告)号：WO2015176244A1
公开(公告)日：2015-11-26
申请号：PCT/CN2014/077979
申请日：2014-05-21
申请人： QUALCOMM INCORPORATED , ZHANG, Le , SU, Wenjun , LEE, Chulkyu
发明人： ZHANG, Le , SU, Wenjun , LEE, Chulkyu
IPC分类号： H03M9/00
CPC分类号： G06F1/324 , G06F1/08 , G06F13/4022 , G06F13/4282 , G11C19/28 , H03M9/00 , Y02D10/14 , Y02D10/151
摘要： Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.
摘要翻译：公开了用于奇数比并行数据总线的串行器和解串器。在一个实施例中，以奇数个并行数据位操作的串行器和解串行器与半速率时钟一起工作，以全时钟速率提供串行数据流。通过提供半速率时钟，集成了串行器的集成电路的功率和面积是保守的。此外，通过提供7：1串行器，该总线现在与MIPI C-PHY标准兼容。

3. 发明申请

WO2015067172A1 CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE 审中-公开
标题翻译：具有增强的交叉和抑制输出通用模式的时钟和数据驱动器
公开(公告)号：WO2015067172A1
公开(公告)日：2015-05-14
申请号：PCT/CN2014/090318
申请日：2014-11-05
申请人： QUALCOMM INCORPORATED , SU, Wenjun , YIN, Guangming , ZHU, Quanqing
发明人： SU, Wenjun , YIN, Guangming , ZHU, Quanqing
IPC分类号： H03K5/12
CPC分类号： H03F3/45762 , H03F1/0277 , H03F3/211 , H03F3/45183 , H03F3/45609 , H03F3/72 , H03F2200/555 , H03F2200/72 , H03F2203/45288 , H03F2203/45301 , H03F2203/45511 , H03F2203/45638 , H03F2203/45644 , H03F2203/45702 , H03K5/12
摘要： Methods, apparatus, and means for maintaining a low output common-mode voltage in a driver are provided. One example apparatus includes a first differential amplifier stage configured to provide a differential output for the apparatus; and a second differential amplifier stage configured to drive the first differential amplifier stage, the second differential amplifier stage including a pair of pre-driver amplifiers, a pair of n-stage circuits, and an input skew averaging circuit, wherein each of the pair of n-stage units is split into two half blocks. The input skew averaging circuit is configured to suppress the output common-mode voltage by driving the blocks with complementary digital inputs to average out a skew in a gate-to-source voltage of the pair of n-stage circuits. For certain aspects, two feed-forward capacitors may be added to enhance the transconductance and operating speed of main transistors of the first differential amplifier stage.
摘要翻译：提供了用于在驱动器中维持低输出共模电压的方法，装置和装置。一个示例性设备包括：第一差分放大器级，被配置为提供用于该设备的差分输出; 以及第二差分放大器级，被配置为驱动所述第一差分放大器级，所述第二差分放大器级包括一对预驱动器放大器，一对n级电路和输入偏差均衡电路，其中， n级单元分为两个半块。输入偏斜平均电路被配置为通过用互补数字输入驱动块来抑制输出共模电压，以平均一对n级电路的栅极至源极电压的偏移。对于某些方面，可以添加两个前馈电容器以增强第一差分放大器级的主晶体管的跨导和工作速度。

4. 发明申请

WO2015066867A1 CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE 审中-公开
标题翻译：具有增强的交叉和抑制输出通用模式的时钟和数据驱动器
公开(公告)号：WO2015066867A1
公开(公告)日：2015-05-14
申请号：PCT/CN2013/086674
申请日：2013-11-07
申请人： QUALCOMM INCORPORATED , SU, Wenjun , YIN, Guangming , ZHU, Quanqing
发明人： SU, Wenjun , YIN, Guangming , ZHU, Quanqing
IPC分类号： H03F3/45
CPC分类号： H03F3/45762 , H03F1/0277 , H03F3/211 , H03F3/45183 , H03F3/45609 , H03F3/72 , H03F2200/555 , H03F2200/72 , H03F2203/45288 , H03F2203/45301 , H03F2203/45511 , H03F2203/45638 , H03F2203/45644 , H03F2203/45702 , H03K5/12
摘要： Maintaining a low output common-mode voltagein a driver is desirable. To maintain the low output common-mode voltage, apparatus, method, and means are proposed as follows: a first differential amplifier stage configured to provide a differential output for the apparatus; and a second differential amplifier stage configured to drive the first differential amplifier stage, the second differential amplifier stage including a pre-driver amplifier, a pair of n-stage units, and an input skew averaging unit, the input skew averaging unit configured to suppress the output common-mode voltage by splitting each of the pair of n-stage units into two half blocks and driving the blocks with complementary digital input to cancel out a skew in a gate-to-source voltage of the pair of n-stage units. Furthermore, two feed-forward capacitors are added to enhance the transconductance and operating speed of main transistors of the first differential amplifier stage.
摘要翻译：在驱动器中维持低输出共模电压是理想的。为了保持低输出共模电压，提出了如下装置，方法和装置：第一差分放大器级，被配置为提供装置的差分输出; 以及第二差分放大器级，被配置为驱动所述第一差分放大器级，所述第二差分放大器级包括预驱动器放大器，一对n级单元和输入偏斜平均单元，所述输入偏斜平均单元被配置为抑制通过将一对n级单元中的每一个分成两个半块并且以互补的数字输入驱动该块以消除该对n级单元的栅极 - 源极电压的偏斜的输出共模电压。此外，添加两个前馈电容器以增强第一差分放大器级的主晶体管的跨导和操作速度。

5. 发明申请

WO2020062099A1 BODY BIASING TO BALANCE RDAC SWITCHES 审中-公开
公开(公告)号：WO2020062099A1
公开(公告)日：2020-04-02
申请号：PCT/CN2018/108485
申请日：2018-09-28
申请人： QUALCOMM INCORPORATED , MIAO, Guoqing , SU, Wenjun , YIN, Guangming , JIANG, Bo
发明人： MIAO, Guoqing , SU, Wenjun , YIN, Guangming , JIANG, Bo
IPC分类号： H03M1/66
摘要： The present disclosure describes aspects of body biasing to balance resistive digital-to-analog converter (RDAC) switches. In some aspects, a unit of an RDAC circuit includes a first switch having a source coupled to a voltage source and a drain coupled to a resistor of the RDAC unit. The RDAC unit also includes a second switch having a source coupled to a lower potential and a drain coupled to the resistor of the RDAC unit. A body biasing circuit provides a bias voltage that is applied to a body terminal of the first switch or the second switch of the RDAC unit. By applying the bias voltage to the body terminal of one or both of the RDAC unit switches, respective on-resistances of the switches can be balanced or matched. This may in turn improve RDAC circuit performance, such as by reducing total harmonic distortion associated with switch on-resistance mismatch.

6. 发明申请

WO2008002792A3 VERSATILE AND COMPACT DC-COUPLED CML BUFFER 审中-公开
公开(公告)号：WO2008002792A3
公开(公告)日：2008-01-03
申请号：PCT/US2007/071496
申请日：2007-06-18
申请人： QUALCOMM INCORPORATED , NARATHONG, Chiewcharn , SU, Wenjun
发明人： NARATHONG, Chiewcharn , SU, Wenjun
IPC分类号： H03K3/356 , H03K19/017 , H03K19/0185
摘要： Differential signal output nodes of a CML buffer (102) are DC-coupled by contiguous conductors to the differential signal input nodes of a load (105) (for example, a CML logic element). The CML buffer (102) includes a pulldown load latch (112) that increases buffer transconductance and that provides a DC bias voltage across the conductors and onto the input nodes of the load (105), thereby obviating the need for the load to have DC biasing circuitry. Capacitors of a conventional AC coupling between buffer and load are not needed, thereby reducing the amount of die area needed to realize the circuit and thereby reducing the capacitance of the buffer-to-load connections. Switching power consumption is low due to the low capacitance buffer-to-load connections. Differential signals can be communicated from buffer to load over a wide frequency range of from less than five kilohertz to more than one gigahertz with less than fifty percent signal attenuation.

7. 发明申请

WO2010060107A1 TECHNIQUES FOR IMPROVING TRANSMITTER PERFORMANCE 审中-公开
标题翻译：改善发射机性能的技术
公开(公告)号：WO2010060107A1
公开(公告)日：2010-05-27
申请号：PCT/US2009/065807
申请日：2009-11-24
申请人： QUALCOMM INCORPORATED , NARATHONG, Chiewcharn , SU, Wenjun
发明人： NARATHONG, Chiewcharn , SU, Wenjun
IPC分类号： H03G3/30 , H03F1/56
CPC分类号： H03G3/3042 , H03F1/56
摘要： Exemplary embodiment are directed to preserving transmitter linearity in RF transceivers while reducing RX band noise for use with low-power voltage supplies. In one aspect, a programmable attenuation element may be provided on-chip at the output of a driver amplifier, prior to a matching network. In another aspect, the programmable attenuation element may include a plurality of switchable capacitors.
摘要翻译：示例性实施例涉及在RF收发器中保持发射机线性度，同时降低用于低功率电源的RX频带噪声。在一个方面，可以在匹配网络之前在驱动器放大器的输出处片上设置可编程衰减元件。在另一方面，可编程衰减元件可以包括多个可切换电容器。

8. 发明申请

WO2008002968A1 LOW-POWER MODULUS DIVIDER STAGE 审中-公开
标题翻译：低功率模块分频器级
公开(公告)号：WO2008002968A1
公开(公告)日：2008-01-03
申请号：PCT/US2007/072215
申请日：2007-06-27
申请人： QUALCOMM Incorporated , NARATHONG, Chiewcharn , SU, Wenjun
发明人： NARATHONG, Chiewcharn , SU, Wenjun
IPC分类号： H03K23/00
CPC分类号： H03K23/54
摘要： A modulus divider stage (MDS) includes first and second stages. The MDS receives a modulus divisor control signal S that determines whether the MDS stage operates in a divide-by-two mode or a divide-by-three mode. The MDS stage also receives a feedback modulus control signal from another MDS. When in the divide-by-two mode, the MDS divides by two regardless of the feedback modulus control signal. To conserve power, the first stage is unpowered when the MDS stage operates in the divide-by-two mode. When in the divide-by-three mode, the MDS stage either divides by two or by three depending on the feedback modulus control signal. To further reduce power consumption, the first stage is unpowered when the MDS stage is in the divide-by-three mode but is nonetheless performing a divide-by-two operation. A power-down transistor holds the output of the first stage at the proper logic level when the first stage is unpowered.
摘要翻译：模数分频器级（MDS）包括第一级和第二级。 MDS接收模数除数控制信号S，其确定MDS级是以二分模式还是三分模式操作。 MDS级还接收来自另一MDS的反馈模数控制信号。在二分模式下，无论反馈模数控制信号如何，MDS均除以二。为了节省功率，当MDS阶段以二分模式运行时，第一级无功。在三分频模式下，根据反馈模数控制信号，MDS级分为2或3。为了进一步降低功耗，当MDS级处于三分频模式时，第一级没有动力，但仍然执行一个二分之一的操作。当第一级无功时，掉电晶体管将第一级的输出保持在适当的逻辑电平。

9. 发明申请

WO2008014282A3 MULTI-MODULUS DIVIDER RETIMING CIRCUIT 审中-公开
公开(公告)号：WO2008014282A3
公开(公告)日：2008-01-31
申请号：PCT/US2007/074257
申请日：2007-07-24
申请人： QUALCOMM INCORPORATED , NARATHONG, Chiewcharn , SU, Wenjun
发明人： NARATHONG, Chiewcharn , SU, Wenjun
IPC分类号： H03K21/10 , H03K23/66
摘要： A multi-modulus divider (MMD) receives an MMD input signal and outputs an MMD output signal SOUT. The MMD includes a chain of modulus divider stages (MDSs). Each MDS receives an input signal, divides it by either two or three, and outputs the result as an output signal. Each MDS responds to its own modulus control signal that controls whether it divides by two or three. In one example, a sequential logic element outputs SOUT. The low jitter modulus control signal of one of the first MDS stages of the chain is used to place a sequential logic element into a first state. The output signal of one of the MDS stages in the middle of the chain is used to place the sequential logic element into a second state. Power consumption is low because the sequential logic element is not clocked at the high frequency of the MMD input signal.

10. 发明申请

WO2011031540A3 HIGH LINEAR FAST PEAK DETECTOR 审中-公开
标题翻译：高线性快速PEAK探测器
公开(公告)号：WO2011031540A3
公开(公告)日：2011-03-17
申请号：PCT/US2010/046915
申请日：2010-08-27
申请人： QUALCOMM Incorporated , SU, Wenjun , HADJICHRISTOS, Aristotele , CASSIA, Marco , NARATHONG, Chiewcharn
发明人： SU, Wenjun , HADJICHRISTOS, Aristotele , CASSIA, Marco , NARATHONG, Chiewcharn
IPC分类号： G01R19/04
摘要： A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.
摘要翻译：描述了具有可变偏置电流和/或可变偏置电压的高线性快速峰值检测器。在示例性设计中，峰值检测器包括晶体管，可变电流源，电容器和反馈电路。晶体管接收输入信号并提供源电流。可变电流源接收输入信号，当输入信号为低时提供高偏置电流，并且当输入信号为高时提供低偏置电流。当输入信号为高电平时，电容器由源电流充电，当输入信号为低电平时，电容器由高偏置电流放电。当输入信号为高时，反馈电路接收来自电容器的检测信号并为晶体管提供更高的偏置电压，这导致来自晶体管的更高的源电流。

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