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1. 发明申请

WO2010081021A1 SYSTEM AND METHOD TO READ AND WRITE DATA AT A MAGNETIC TUNNEL JUNCTION ELEMENT 审中-公开
标题翻译：在磁性隧道连接元件上读取和写入数据的系统和方法
公开(公告)号：WO2010081021A1
公开(公告)日：2010-07-15
申请号：PCT/US2010/020524
申请日：2010-01-08
申请人： QUALCOMM INCORPORATED , ABU-RAHMA, Mohamed, Hassan , SONG, Seung-Chul , YOON, Sei, Seung , PARK, Dongkyu , ZHONG, Cheng , DAVIERWALLA, Anosh, B.
发明人： ABU-RAHMA, Mohamed, Hassan , SONG, Seung-Chul , YOON, Sei, Seung , PARK, Dongkyu , ZHONG, Cheng , DAVIERWALLA, Anosh, B.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1657 , G11C11/1659 , G11C11/1673
摘要： A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device (100) includes a spin transfer torque magnetic tunnel junction (STT-MT J) element (102) and a transistor (104) with a first gate (106) and a second gate (108) coupled to the STT-MTJ element.
摘要翻译：公开了一种在磁随机存取存储器中读取和写入数据的系统和方法。在特定实施例中，装置（100）包括自旋转移转矩磁隧道结（STT-MTJ）元件（102）和具有第一栅极（106）和第二栅极（108）的晶体管（104） STT-MTJ元素。

2. 发明申请

WO2010077611A1 DIGITALLY-CONTROLLABLE DELAY FOR SENSE AMPLIFIER 审中-公开
标题翻译：用于感应放大器的数字控制延时
公开(公告)号：WO2010077611A1
公开(公告)日：2010-07-08
申请号：PCT/US2009/066999
申请日：2009-12-07
申请人： QUALCOMM INCORPORATED , PARK, Dongkyu , DAVIERWALLA, Anosh B. , ZHONG, Cheng , ABU-RAHMA, Mohamed Hassan Soliman , YOON, Sei Seung
发明人： PARK, Dongkyu , DAVIERWALLA, Anosh B. , ZHONG, Cheng , ABU-RAHMA, Mohamed Hassan Soliman , YOON, Sei Seung
IPC分类号： G11C7/06 , G11C7/22 , G11C11/16
CPC分类号： G11C7/22 , G11C7/06 , G11C11/1673 , G11C11/1693 , G11C2207/065 , G11C2207/2281
摘要： Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. A circuit includes a sense amplifier (160), having a first input (162), a second input (164), and an enable input (166); a first amplifier (132) coupled to an output of a magnetic resistance-based memory cell (112); a second amplifier (134) coupled to a reference output of the cell; and a digitally-controllable amplifier (136) coupled to a tracking circuit cell (116) that is similar to the cell of the MRAM. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit (150). The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal (152) from the digitally-controllable amplifier via the logic circuit.
摘要翻译：公开了在读取磁随机存取存储器（MRAM）装置中插入可选延迟的电路，装置和方法。电路包括具有第一输入（162），第二输入（164）和使能输入（166）的读出放大器（160）。耦合到基于磁阻的存储单元（112）的输出端的第一放大器（132）; 耦合到所述单元的参考输出的第二放大器（134）以及耦合到类似于MRAM的单元的跟踪电路单元（116）的数字可控放大器（136）。读出放大器的第一输入耦合到第一放大器，读出放大器的第二输入耦合到第二放大器，而使能输入经由逻辑电路（150）耦合到第三数字可控放大器。一旦感测放大器从数字可控放大器经由逻辑电路接收到使能信号（152），读出放大器可以基于从基于磁阻的存储单元和参考单元的输出接收的放大值来产生输出值。

3. 发明申请

WO2010030531A1 MEMORY DEVICE FOR RESISTANCE-BASED MEMORY APPLICATIONS 审中-公开
标题翻译：用于基于电阻的存储器应用的存储器件
公开(公告)号：WO2010030531A1
公开(公告)日：2010-03-18
申请号：PCT/US2009/055617
申请日：2009-09-01
申请人： QUALCOMM INCORPORATED , DAVIERWALLA, Anosh B. , ZHONG, Cheng , PARK, Dongkyu , ABU-RAHMA, Mohamed Hassan , SANI, Mehdi Hamidi , YOON, Sei Seung
发明人： DAVIERWALLA, Anosh B. , ZHONG, Cheng , PARK, Dongkyu , ABU-RAHMA, Mohamed Hassan , SANI, Mehdi Hamidi , YOON, Sei Seung
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C7/14 , G11C11/16
CPC分类号： G11C11/1673
摘要： In a particular embodiment, a memory device (100) is disclosed that includes a memory cell (226) including a resistance based memory element (228) coupled to an access transistor (230). The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier (202) configured to couple the memory cell to a supply voltage (Vamp) that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor (216) that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.
摘要翻译：在特定实施例中，公开了一种包括存储单元（226）的存储器件（100），该存储器单元包括耦合到存取晶体管（230）的基于电阻的存储元件（228）。存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。存储器件还包括被配置为将存储器单元耦合到大于电压限制的电源电压（Vamp）的第一放大器（202），以基于通过存储器单元的电流产生数据信号。第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管（216）。钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。

4. 发明申请

WO2010132875A1 SYSTEMS AND METHODS FOR PRODUCING A PREDETERMINED OUTPUT IN A SEQUENTIAL CIRCUIT DURING POWER ON 审中-公开
标题翻译：在通电期间在顺序电路中生成预测输出的系统和方法
公开(公告)号：WO2010132875A1
公开(公告)日：2010-11-18
申请号：PCT/US2010/035084
申请日：2010-05-17
申请人： QUALCOMM INCORPORATED , BELLUR, Kashyap, R. , DAVIERWALLA, Anosh, B. , HOLENSTEIN, Christian
发明人： BELLUR, Kashyap, R. , DAVIERWALLA, Anosh, B. , HOLENSTEIN, Christian
IPC分类号： H03K19/00 , H03K19/0185
CPC分类号： H03K19/0013 , H03K17/22 , H03K19/018521
摘要： An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage.
摘要翻译：公开了一种被配置为在通电期间在顺序电路中产生预定输出的集成电路。集成电路包括耦合到一个或多个内部节点的一个或多个电容器。如果电源节点处的电压以一段时间或更快的速度上升到设定电压，则一个或多个电容器对内部节点进行充电。集成电路还包括耦合到电源节点的第一晶体管。当电源节点上的电压上升到设定电压时，第一晶体管产生对一个或多个内部节点充电的泄漏电流，不会比时间段更快。集成电路还包括输出节点。输出节点上的逻辑值基于充电内部节点上的逻辑值，当时序电路的输入信号不起作用并且电源节点上的电压处于设定电压时。

5. 发明申请

WO2010088661A1 SYSTEM AND METHOD OF PULSE GENERATION 审中-公开
标题翻译：脉冲发生系统与方法
公开(公告)号：WO2010088661A1
公开(公告)日：2010-08-05
申请号：PCT/US2010/022875
申请日：2010-02-02
申请人： QUALCOMM INCORPORATED , RAO, Hari , DAVIERWALLA, Anosh, B. , PARK, Dongkyu , YOON, Sei, Seung
发明人： RAO, Hari , DAVIERWALLA, Anosh, B. , PARK, Dongkyu , YOON, Sei, Seung
IPC分类号： G11C7/22 , G11C16/12 , H03K7/08 , H04L7/033
CPC分类号： G11C7/22 , G11C7/04 , G11C16/12 , H03K2005/00293
摘要： In a particular embodiment, a device (102) includes a reference voltage circuit (110) to generate a controlled voltage. The device includes a frequency circuit (106) configured to generate a frequency output signal (328) having a pre-set frequency and a counter (304) to generate a count signal (310) based on the pre-set frequency. The device also includes a delay circuit (306) coupled to receive the count signal and to produce a delayed digital output signal (312) and a latch (320) to generate a pulse (130). The pulse has a first edge (132) responsive to a write command and a trailing edge (134) formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold.
摘要翻译：在特定实施例中，设备（102）包括用于产生受控电压的参考电压电路（110）。该装置包括频率电路（106），其被配置为产生具有预置频率的频率输出信号（328）和计数器（304），以基于预设频率产生计数信号（310）。该装置还包括一个延迟电路（306），用于接收该计数信号并产生延迟的数字输出信号（312）和一个锁存器（320）以产生脉冲（130）。脉冲响应于写入命令和响应于延迟的数字输出信号形成的后沿（134），具有第一边沿（132）。在特定实施例中，脉冲的脉冲宽度对应于超过临界电流的施加的电流电平，以使得能够将数据写入存储器的元件但不超过预定阈值。

6. 发明申请

WO2009111208A1 MULTIPLE TRANSMITTER SYSTEM AND METHOD 审中-公开
标题翻译：多传输系统和方法
公开(公告)号：WO2009111208A1
公开(公告)日：2009-09-11
申请号：PCT/US2009/034943
申请日：2009-02-24
申请人： QUALCOMM INCORPORATED , LEE, Chulkyu , DAVIERWALLA, Anosh B. , WILEY, George A.
发明人： LEE, Chulkyu , DAVIERWALLA, Anosh B. , WILEY, George A.
IPC分类号： H04L5/20 , H04L25/02
CPC分类号： H04L25/0272 , H04L25/49
摘要： Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.
摘要翻译：公开了数据传输的系统和方法。在一个实施例中，选择性地激活至少两个发射机，并且至少一个发射机在串行接口处被去激活，以经由至少两条不同的线路传输数据。

7. 发明申请

WO2009097372A1 DIFFERENTIAL AMPLIFIER WITH ACCURATE INPUT OFFSET VOLTAGE 审中-公开
标题翻译：具有精确输入偏置电压的差分放大器
公开(公告)号：WO2009097372A1
公开(公告)日：2009-08-06
申请号：PCT/US2009/032308
申请日：2009-01-29
申请人： QUALCOMM Incorporated , DAVIERWALLA, Anosh B. , LEE, Chul Kyu , DANG, Vannam
发明人： DAVIERWALLA, Anosh B. , LEE, Chul Kyu , DANG, Vannam
IPC分类号： H03F3/45 , H03K5/24
CPC分类号： H03F3/45183 , H03F3/45192 , H03F3/45766 , H03F2200/453 , H03F2200/456 , H03F2203/45028 , H03F2203/45048 , H03F2203/45286 , H03F2203/45291 , H03F2203/45294 , H03F2203/45624 , H03F2203/45628 , H03K5/2481
摘要： An amplifier (209) ( with accurate input offset voltage is described. In one design, the amplifier includes first and s (312, 314) receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair (322, 324) receives a differential reference signal (Vref p, Vref n) and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal Ioutp, lout n) The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.
摘要翻译：在一个设计中，放大器包括第一和第（312,314）接收差分输入信号并提供第一差分电流信号，第二不平衡差动对（322， 324）接收差分参考信号（Vref p，Vref n），并提供第二差分电流信号，其从第一差分电流信号中减去以获得差分输出信号Ioutp，lout n）第二差分电流信号跟踪误差当差分输入信号等于放大器的目标输入失调电压时，差分输出信号为零。对于每个不平衡差分对，一个晶体管是另一个晶体管尺寸的M倍，其中M被选择以获得目标输入偏移电压。

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